VME Scon SEL2, GAP4, GAP3, GAP2, GAP1, GAP0 | Emerson MVME2500

Controls, LEDs, and Connectors

Note that this switch is wired in parallel with the geographical address pins on the 5-row connector. These switches must be in the "OFF" position when installed in a 5-row chassis in order to get the correct address from the P1 connector. This switch also includes the SCON control switches.

Figure 3-5 Geographical Address Switch

Table 3-19 Geographical Address Switch

Position	Function	Default

S1-1	VME SCON Auto1	Auto-SCON
S1-2	VME SCON SEL2	Non-SCON
S1-3	GAP	1

S1-4	GAP4	1

S1-5	GAP3	1

S1-6	GAP2	1

S1-7	GAP1	1

S1-8	GAP0	1

1. The VME SCON MAN switch is "OFF" to select Auto-SCON mode. The switch is "ON" to select manual SCON mode whichworks in conjunction with the VME SCON SEL switch.

2. The VME SCON SEL switch is OFF to select non-SCON mode. The switch is ON to select always SCON mode. This switch is only effective when the VME SCON MAN switch is "ON".

58	MVME2500 Installation and Use (6806800L01H)

Image 58

Emerson MVME2500 manual VME Scon SEL2, GAP4, GAP3, GAP2, GAP1, GAP0

Contents

MVME2500 Contact Address Contents Contents Contents Memory Maps and Registers Emerson Network Power Embedded Computing Documents Safety Notes Sicherheitshinweise Index List of Tables List of Tables List of Figures Figure A-1 List of Figures About this Manual Overview of ContentsAbbreviations About this Manual Vita ConventionsUSB VME About this Manual About this Manual Summary of Changes Documentation, on Introduction Key Features of the MVME2500Overview KB Mram Introduction 8 KB VPD Eeprom Standard Compliances Board Standard Compliances Mechanical Data Mechanical DataOrdering Information Available Board Variants VME-64GBSSDKIT Available Board AccessoriesVME-HDMNTKIT SERIAL-MINI-D Product Identification Serial Number Location Hardware Preparation and Installation Unpacking and Inspecting the Board Hardware Preparation and InstallationRequirements Environmental Requirements Environmental RequirementsGrms Power Requirements Power Requirements Configuring the Board Equipment Requirements Installing Accessories Rear Transition Module Installation Procedure 2 PMC/XMC Support Installing and Removing the Board Hardware Preparation and Installation Completing the Installation Controls, LEDs, and Connectors Board Layout Controls, LEDs, and Connectors Front Panel LEDs Reset SwitchFront Panel LEDs GENET1 TSEC1 UserFail Speed Onboard LEDs ConnectorsOnboard LEDs Status Front Panel Tri-Speed Ethernet Connector J1 Front Panel Connectors1.1 RJ45 with Integrated Magnetics J1 Front Panel Serial Port J4 Front Panel Serial Port J4 USB Connector J5 Controls, LEDs, and Connectors USB Connector J5VMEBus P1 Connector VMEbus P1 Connector GA3 Dtack DS0 BR1 Lword GA2 Write BR2GND BR3 GA4 Controls, LEDs, and Connectors VMEBus P2 Connector VMEbus P2 Connector Flash Program Connector P7 Onboard ConnectorsFlash Programming Header P7 GND Sata Power Enable Sata TX + Sata Detect Sata Connector J3Custom Sata Connector J3 Sata RX PMC Connectors 10 PMC J11 Connector 11 PMC J12 Connector 12 PMC J13 Connector GND CBE7 CBE6 CBE5 CBE4 PAR64 13 PMC J14 Connector Jtag Connector P6 14 Jtag Connector P6 Scan 3 TCK GPO0 Scan 2 TMS Scan 2 TDO Scan 2 TCKGND Scan 2 TDI Scan 3 TMS Scan 3 TCK1 Scan 3 TDO GND Scan 4 TDI Scan 4 TCK Scan 4 Trst Scan 5 TMS Scan 5 TDO 16 SD Connector J2 Controls, LEDs, and Connectors COP Connector P6SD Connector J2 15 COP Header P10 XMC Connector XJ2 17 XMC Connector XJ2 Pinout Miscellaneous P2020 Debug Connectors 18 P20x0 Debug Header Geographical Address Switch S1 SwitchesTrigin MSRCID4 GND GAP3 VME Scon SEL2GAP4 GAP2 SMT Configuration Switch S2 Gbemuxsel MasterwpdisaBled Plane Functional Description Block DiagramChipset Integrated Memory Controller 1 e500 Processor CoreFunctional Description Secure Digital Hub Controller Sdhc PCI Express InterfaceLocal Bus Controller LBC 6 I2C Interface Enhanced Three-Speed Ethernet Controller eTSEC DuartDMA Controller General Purpose I/O Gpio System Memory Timers14 P20x0 Hardware Configuration Pins Common On-Chip Processor COP Fpga Tick Timer Internal TimerWatchdog Timer Ethernet Interfaces SPI Flash Memory SPI Bus InterfaceSPI Flash Programming Firmware Redundancy SPI Device Multiplexing Logic Crisis Recovery Front Uart Control Rear Uart Control PMC/XMC Sites PMC Add-on Card Sata InterfaceXMC Add-on Card 13 I2C Devices VME Support12 USB 11.1 Tsi148 VME Controller Onboard Voltage Supply Requirement Reset/Control FpgaPower Management Voltage Supply Requirement Power Up Sequencing Requirements Reset Structure Clock Structure Thermal Management Real-Time Clock BatteryReset Sequence Thermal Interrupt Threshold Debugging Support Post Code IndicatorPost Code Indicator on the LED Jtag Chain and Board Custom Debugging Transition Module FeaturesRear Transition Module RTM SBC Functional Description Memory Map Memory Maps and RegistersPhysical Address Map Memory Maps and Registers Flash Memory MapLinux Devices Memory Map Flash Memory Map Linux Devices Memory Map PLD Year Register Programmable Logic Device PLD RegistersPLD Revision Register PLD Revision Register PLD Day Register PLD Month RegisterPLD Sequence Register Wrgd RGD Pwrg Oper Reset PLD Power Good Monitor RegisterPLD Power Good Monitor Register Rsvd Pwrv 10 PLD LED Control Register PLD LED Control RegisterPWRV1P2SWPWRG 11 PLD PCI/PMC/XMC Monitor Register PLD PCI/PMC/XMC Monitor RegisterPMC1PN 12 PLD U-Boot and TSI Monitor Register PLD U-Boot and TSI Monitor RegisterPLD Boot Bank Register 13 PLD Boot Bank Register Bootb Boots Locka 14 PLD Write Protect and I2C Debug Register Wpdi WPN Ugen Flash Sabled Oper ResetPLD Write Protect and I2C Debug Register Rsvd Master Flash I2CDEB Serial I2CDEBUGEN=0 15 PLD Test Register PLD Test Register16 PLD Test Register PLD GPIO2 Interrupt Register Rsvd NMI TICK0INT TICK1INT TICK2INT Oper Reset17 PLD GPIO2 Interrupt Register Cpureset Wdtime Lrsto PLD Shutdown and Reset Control and Reset Reason Register18 PLD Shutdown and Reset Control and Reset Reason Register Dnmask OUT Oper Reset PLD Watchdog Timer Refresh Register 19 PLD Watchdog Timer Refresh Register PLD Watchdog Control Register PLD Watchdog Timer Count Register21 PLD Watchdog Timer Count Register 20 PLD Watchdog Control Register Prescaler Register External Timer Registers22 Prescaler Register 23 Control Registers COC ENC Oper ResetControl Registers Ints Cint 24 Compare High Word Registers Compare High and Low Word Registers25 Compare Low Word Registers 26 Counter High Word Registers Counter High and Low Word Registers27 Counter Low Word Registers 102 Boot System Accessing U-Boot Booting from a Network Boot OptionsBoot System Booting from an Optional Sata Drive Booting from a USB Drive Booting from an SD Card Booting VxWorks Through the Network Using the Persistent Memory Feature Analyzing Kernel Log Files after a Kernel Panic MVME2500 Specific U-Boot Commands MVME2500 Specific U-Boot Commands Boot System Updating U-Boot Sf probe 112 POR Configuration Settings Reset ConfigurationProgramming Model Programming Model Ecmdc Config Config Pins Selection Remarks ETSEC2 Sgmii LGPL1ETSEC3 Sgmmi TSEC1588ALARM ETSEC1 TSEC1TXD0 LWE1/LBS1 Config Config Pins Selection Remarks Boot ROMTSEC1TXER TSEC2TXER Interrupt Controller MVME2500 Interrupt List I2C Bus Device Addressing I2C Bus Device AddressingEthernet PHY Address PHY Types and MII Management Bus Address Quad Uart Other Software ConsiderationsMram TSEC3 LBC Timing Parameters LBC Timing Parameters Clock Distribution Clock Distribution System Clock System Clock Real Time Clock Input Local Bus Controller Clock Divisor 124 Replacing the Battery Replacing the Battery Replacing the Battery Replacement Procedure 128 Emerson Network Power Embedded Computing Documents Related Documentation Manufacturers’ Documents Related SpecificationsTable B-3 Related Specifications Related Documentation PCI-SIG SATA-IO 132 Safety Notes EMC Results pending testing Safety Notes InstallationOperation Cabling and Connectors Battery Sicherheitshinweise Betrieb Sicherheitshinweise 139 Kabel und Stecker Batterie Umweltschutz 142 Index Index Page HOW to Reach Literature and Technical Support