Emerson MVME2500 manual PCI Express Interface, Local Bus Controller LBC, 4.2.6 I2C Interface

Models: MVME2500

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Functional Description

Automatic DRAM initialization sequence or software-controlled initialization sequence and automatic DRAM data initialization.

Write leveling for DDR3 memories and supports up to eight posted refreshes.

4.2.3PCI Express Interface

The PCI Express interface is compatible with the PCI Express Base Specification Rev. 1.0a. The PCI Express controller connects the internal platform to a 2.5 GHz serial interface. The P20x0 has the options for up to three PCI-E interfaces with up to x4 link width. The PCI-E controller can be configured to operate as either PCI-E root complex (RC) or as an endpoint (EP) device.

4.2.4Local Bus Controller (LBC)

The main component of the enhanced LBC is the memory controller that provides a 16-bit interface to various types of memory devices and peripherals. The memory controller is responsible for controlling eight memory banks shared by the following: a general purpose chip select machine (GPCM); a flash controller machine (FCM) and user programmable machines (UPMs).

4.2.5Secure Digital Hub Controller (SDHC)

The SDHC/eSDHC provides an interface between the host system and the memory cards such as the MMC and SD. It is compatible with the SD Host Controller Standard Specification Ver. 2.0 and supports the following: SD, miniSD, SD Combo, MMC+ and RS-MMC card.

4.2.6I2C Interface

The MVME2500 uses only one of the two independent I2C buses on the processor. For more information, see I2C Devices, on page 73.

4.2.7USB Interface

The P20x0 implements a USB 2.0 compliant serial interface engine. For more information, see USB, on page 73.

MVME2500 Installation and Use (6806800L01H)

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Emerson MVME2500 PCI Express Interface, Local Bus Controller LBC, Secure Digital Hub Controller SDHC, 4.2.6 I2C Interface