System Clock | Emerson MVME2500 specification

Programming Model

Table 7-6 Clock Distribution (continued)

Device	Clock Signal	Frequency	Clock Tree Source	VIO

BCM54616S	SW_25MHZ_CLK	25Mhz	ICS83905AGILF	+3.3V

XMC	CLK_XMC1	100MHz	ICS9FG108	DIFF

QorIQ P20x0	SD_REF_CLK	100MHz	ICS9FG109	DIFF

TSI384	CLK_PCIEC1	100MHz	ICS9FG110	DIFF

TSI384	CLK_PCIEC3	100MHz	ICS9FG111	DIFF

88SE6121	CLK_88SE6121_PCIE_100MH	100MHz	ICS9FG112	DIFF
	Z

FPGA	CLK_CPLD	1.8432MHz	Oscillator	+3.3V

USB	CLK_USB_1_24MHZ	24MHz	Oscillator	+3.3V

QorIQ P20x0	CPU_RTC	1MHz	FPGA	+3.3V

PMC	CLK_PMC1	33/66/100/133M	TSI384	+3.3V
		hz

TSI148	CLK_PCI_BR3	133Mhz	ICS840S07I	+3.3V

RTC	CLK_32K	32.768KHz	DS32KHz	+3.3V

FPGA	CPU_LCK0	25MHz	QorIQ P20x0	+3.3V

QUART	CLK_QUART	1.8432MHz	FPGA	+3.3V

ICS83905	CLK_25MHZ_ICS9FG108	25Mhz	ICS83905AGILF	+3.3V

7.7.1System Clock

The system and DDR clock is driven by ICS840S07I. The following table defines the clock frequency.

Table 7-7 System Clock

SYSCLK	CORE	CCB Clock (Platform)	DDR3	LBC

100MHz	800/1200 MHz	400 MHz	400MHz	25MHz

122	MVME2500 Installation and Use (6806800L01H)

Image 122

Emerson MVME2500 manual System Clock

Contents

MVME2500 Contact Address Contents Contents Contents Memory Maps and Registers Emerson Network Power Embedded Computing Documents Safety Notes Sicherheitshinweise Index List of Tables List of Tables List of Figures Figure A-1 List of Figures Abbreviations Overview of ContentsAbout this Manual About this Manual Vita ConventionsUSB VME About this Manual About this Manual Summary of Changes Documentation, on Overview Key Features of the MVME2500Introduction  8 KB VPD Eeprom IntroductionKB Mram Standard Compliances Board Standard Compliances Mechanical Data Mechanical DataOrdering Information Available Board Variants VME-64GBSSDKIT Available Board AccessoriesVME-HDMNTKIT SERIAL-MINI-D Product Identification Serial Number Location Hardware Preparation and Installation Requirements Hardware Preparation and InstallationUnpacking and Inspecting the Board Grms Environmental RequirementsEnvironmental Requirements Power Requirements Power Requirements Configuring the Board Equipment Requirements Installing Accessories Rear Transition Module Installation Procedure 2 PMC/XMC Support Installing and Removing the Board Hardware Preparation and Installation Completing the Installation Controls, LEDs, and Connectors Board Layout Controls, LEDs, and Connectors Front Panel Front Panel LEDs Reset SwitchLEDs GENET1 TSEC1 UserFail Speed Onboard LEDs Status ConnectorsOnboard LEDs 1.1 RJ45 with Integrated Magnetics J1 Front Panel ConnectorsFront Panel Tri-Speed Ethernet Connector J1 Front Panel Serial Port J4 Front Panel Serial Port J4 USB Connector J5 Controls, LEDs, and Connectors USB Connector J5VMEBus P1 Connector VMEbus P1 Connector GA3 Dtack DS0 BR1 Lword GA2 Write BR2GND BR3 GA4 Controls, LEDs, and Connectors VMEBus P2 Connector VMEbus P2 Connector Flash Programming Header P7 Onboard ConnectorsFlash Program Connector P7 GND Sata Power Enable Sata TX + Sata Detect Sata Connector J3Custom Sata Connector J3 Sata RX PMC Connectors 10 PMC J11 Connector 11 PMC J12 Connector 12 PMC J13 Connector GND CBE7 CBE6 CBE5 CBE4 PAR64 13 PMC J14 Connector Jtag Connector P6 14 Jtag Connector P6 Scan 3 TCK GPO0 Scan 2 TMS Scan 2 TDO Scan 2 TCKGND Scan 2 TDI Scan 3 TMS Scan 3 TCK1 Scan 3 TDO GND Scan 4 TDI Scan 4 TCK Scan 4 Trst Scan 5 TMS Scan 5 TDO 16 SD Connector J2 Controls, LEDs, and Connectors COP Connector P6SD Connector J2 15 COP Header P10 XMC Connector XJ2 17 XMC Connector XJ2 Pinout Miscellaneous P2020 Debug Connectors 18 P20x0 Debug Header Trigin MSRCID4 GND SwitchesGeographical Address Switch S1 GAP3 VME Scon SEL2GAP4 GAP2 SMT Configuration Switch S2 Gbemuxsel MasterwpdisaBled Plane Chipset Block DiagramFunctional Description Functional Description 1 e500 Processor CoreIntegrated Memory Controller Secure Digital Hub Controller Sdhc PCI Express InterfaceLocal Bus Controller LBC 6 I2C Interface Enhanced Three-Speed Ethernet Controller eTSEC DuartDMA Controller General Purpose I/O Gpio System Memory Timers14 P20x0 Hardware Configuration Pins Common On-Chip Processor COP Fpga Tick Timer Internal TimerWatchdog Timer Ethernet Interfaces SPI Flash Programming SPI Bus InterfaceSPI Flash Memory Firmware Redundancy SPI Device Multiplexing Logic Crisis Recovery Front Uart Control Rear Uart Control PMC/XMC Sites XMC Add-on Card Sata InterfacePMC Add-on Card 13 I2C Devices VME Support12 USB 11.1 Tsi148 VME Controller Onboard Voltage Supply Requirement Reset/Control FpgaPower Management Voltage Supply Requirement Power Up Sequencing Requirements Reset Structure Clock Structure Thermal Management Real-Time Clock BatteryReset Sequence Thermal Interrupt Threshold Debugging Support Post Code IndicatorPost Code Indicator on the LED Jtag Chain and Board Custom Debugging Transition Module FeaturesRear Transition Module RTM SBC Functional Description Physical Address Map Memory Maps and RegistersMemory Map Memory Maps and Registers Flash Memory MapLinux Devices Memory Map Flash Memory Map Linux Devices Memory Map PLD Year Register Programmable Logic Device PLD RegistersPLD Revision Register PLD Revision Register PLD Sequence Register PLD Month RegisterPLD Day Register Wrgd RGD Pwrg Oper Reset PLD Power Good Monitor RegisterPLD Power Good Monitor Register Rsvd Pwrv PWRV1P2SWPWRG PLD LED Control Register10 PLD LED Control Register PMC1PN PLD PCI/PMC/XMC Monitor Register11 PLD PCI/PMC/XMC Monitor Register 12 PLD U-Boot and TSI Monitor Register PLD U-Boot and TSI Monitor RegisterPLD Boot Bank Register 13 PLD Boot Bank Register Bootb Boots Locka 14 PLD Write Protect and I2C Debug Register Wpdi WPN Ugen Flash Sabled Oper ResetPLD Write Protect and I2C Debug Register Rsvd Master Flash I2CDEB Serial I2CDEBUGEN=0 16 PLD Test Register PLD Test Register15 PLD Test Register 17 PLD GPIO2 Interrupt Register Rsvd NMI TICK0INT TICK1INT TICK2INT Oper ResetPLD GPIO2 Interrupt Register Cpureset Wdtime Lrsto PLD Shutdown and Reset Control and Reset Reason Register18 PLD Shutdown and Reset Control and Reset Reason Register Dnmask OUT Oper Reset PLD Watchdog Timer Refresh Register 19 PLD Watchdog Timer Refresh Register PLD Watchdog Control Register PLD Watchdog Timer Count Register21 PLD Watchdog Timer Count Register 20 PLD Watchdog Control Register 22 Prescaler Register External Timer RegistersPrescaler Register 23 Control Registers COC ENC Oper ResetControl Registers Ints Cint 25 Compare Low Word Registers Compare High and Low Word Registers24 Compare High Word Registers 27 Counter Low Word Registers Counter High and Low Word Registers26 Counter High Word Registers 102 Boot System Accessing U-Boot Boot System Boot OptionsBooting from a Network Booting from an Optional Sata Drive Booting from a USB Drive Booting from an SD Card Booting VxWorks Through the Network Using the Persistent Memory Feature Analyzing Kernel Log Files after a Kernel Panic MVME2500 Specific U-Boot Commands MVME2500 Specific U-Boot Commands Boot System Updating U-Boot Sf probe 112 Programming Model Reset ConfigurationPOR Configuration Settings Programming Model Ecmdc Config Config Pins Selection Remarks ETSEC2 Sgmii LGPL1ETSEC3 Sgmmi TSEC1588ALARM ETSEC1 TSEC1TXD0 LWE1/LBS1 Config Config Pins Selection Remarks Boot ROMTSEC1TXER TSEC2TXER Interrupt Controller MVME2500 Interrupt List I2C Bus Device Addressing I2C Bus Device AddressingEthernet PHY Address PHY Types and MII Management Bus Address Quad Uart Other Software ConsiderationsMram TSEC3 LBC Timing Parameters LBC Timing Parameters Clock Distribution Clock Distribution System Clock System Clock Real Time Clock Input Local Bus Controller Clock Divisor 124 Replacing the Battery Replacing the Battery Replacing the Battery Replacement Procedure 128 Emerson Network Power Embedded Computing Documents Related Documentation Manufacturers’ Documents Related SpecificationsTable B-3 Related Specifications Related Documentation PCI-SIG SATA-IO 132 Safety Notes EMC Results pending testing Operation InstallationSafety Notes Cabling and Connectors Battery Sicherheitshinweise Betrieb Sicherheitshinweise 139 Kabel und Stecker Batterie Umweltschutz 142 Index Index Page HOW to Reach Literature and Technical Support