PLD Write Protect and I2C Debug Register | Emerson MVME2500 instruction

Memory Maps and Registers

5.5.11 PLD Write Protect and I2C Debug Register

The MVME2500 PLD provides an 8-bit register which is used to indicate the status of I2C and SPI write-protect manual switches and is used to control the SPI write-enable. I2C debug ports are also provided in this register which can be used in controlling the bus’ status.

Table 5-14 PLD Write Protect and I2C Debug Register

REG	PLD Write Protect I2C Debug- 0xFFDF0054

Bit	7	6	5		4	3	2	1	0

Field	RSVD	MASTER	FLASH_		I2C_DEB	SERIAL_	RSVD	I2C_1_	I2C_1_C
		_WP_DI	WP_N		UG_EN	FLASH_		D
		SABLED				WP

OPER	R	R	R		R/W	R/W	R	R/W	R/W

RESET	0	1	0		0	1	0	1	1

Field Description
MASTER_WP_DISABLED			I2C devices manual switch write-protect status
			1	- Write-protect enabled
			0	- Write-protect disabled
FLASH_WP_N			SPI devices manual switch write-protect status
			1	- Write-protect disabled
			0	- Write-protect enabled

MVME2500 Installation and Use (6806800L01H)

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Image 91

Emerson MVME2500 manual PLD Write Protect and I2C Debug Register, Rsvd Master Flash I2CDEB Serial

Contents

MVME2500 Contact Address Contents Contents Contents Memory Maps and Registers Emerson Network Power Embedded Computing Documents Safety Notes Sicherheitshinweise Index List of Tables List of Tables Figure A-1 List of Figures List of Figures About this Manual Overview of ContentsAbbreviations About this Manual VME ConventionsUSB Vita About this Manual About this Manual Summary of Changes Documentation, on Introduction Key Features of the MVME2500Overview KB Mram Introduction 8 KB VPD Eeprom Board Standard Compliances Standard Compliances Available Board Variants Mechanical DataOrdering Information Mechanical Data SERIAL-MINI-D Available Board AccessoriesVME-HDMNTKIT VME-64GBSSDKIT Serial Number Location Product Identification Hardware Preparation and Installation Unpacking and Inspecting the Board Hardware Preparation and InstallationRequirements Environmental Requirements Environmental RequirementsGrms Power Requirements Power Requirements Equipment Requirements Configuring the Board Rear Transition Module Installing Accessories 2 PMC/XMC Support Installation Procedure Installing and Removing the Board Hardware Preparation and Installation Completing the Installation Board Layout Controls, LEDs, and Connectors Front Panel Controls, LEDs, and Connectors LEDs Reset SwitchFront Panel LEDs Speed UserFail GENET1 TSEC1 Onboard LEDs ConnectorsOnboard LEDs Status Front Panel Tri-Speed Ethernet Connector J1 Front Panel Connectors1.1 RJ45 with Integrated Magnetics J1 Front Panel Serial Port J4 Front Panel Serial Port J4 VMEbus P1 Connector Controls, LEDs, and Connectors USB Connector J5VMEBus P1 Connector USB Connector J5 GA4 DS0 BR1 Lword GA2 Write BR2GND BR3 GA3 Dtack VMEbus P2 Connector Controls, LEDs, and Connectors VMEBus P2 Connector Flash Program Connector P7 Onboard ConnectorsFlash Programming Header P7 Sata RX Sata Connector J3Custom Sata Connector J3 GND Sata Power Enable Sata TX + Sata Detect 10 PMC J11 Connector PMC Connectors 11 PMC J12 Connector 12 PMC J13 Connector PAR64 GND CBE7 CBE6 CBE5 CBE4 13 PMC J14 Connector 14 Jtag Connector P6 Jtag Connector P6 GND Scan 4 TDI Scan 4 TCK Scan 4 Trst Scan 5 TMS Scan 5 TDO GPO0 Scan 2 TMS Scan 2 TDO Scan 2 TCKGND Scan 2 TDI Scan 3 TMS Scan 3 TCK1 Scan 3 TDO Scan 3 TCK 15 COP Header P10 Controls, LEDs, and Connectors COP Connector P6SD Connector J2 16 SD Connector J2 17 XMC Connector XJ2 Pinout XMC Connector XJ2 18 P20x0 Debug Header Miscellaneous P2020 Debug Connectors Geographical Address Switch S1 SwitchesTrigin MSRCID4 GND GAP2 VME Scon SEL2GAP4 GAP3 SMT Configuration Switch S2 Plane MasterwpdisaBled Gbemuxsel Functional Description Block DiagramChipset Integrated Memory Controller 1 e500 Processor CoreFunctional Description 6 I2C Interface PCI Express InterfaceLocal Bus Controller LBC Secure Digital Hub Controller Sdhc General Purpose I/O Gpio DuartDMA Controller Enhanced Three-Speed Ethernet Controller eTSEC Common On-Chip Processor COP Timers14 P20x0 Hardware Configuration Pins System Memory Ethernet Interfaces Internal TimerWatchdog Timer Fpga Tick Timer SPI Flash Memory SPI Bus InterfaceSPI Flash Programming Firmware Redundancy SPI Device Multiplexing Logic Front Uart Control Crisis Recovery PMC/XMC Sites Rear Uart Control PMC Add-on Card Sata InterfaceXMC Add-on Card 11.1 Tsi148 VME Controller VME Support12 USB 13 I2C Devices Voltage Supply Requirement Reset/Control FpgaPower Management Onboard Voltage Supply Requirement Power Up Sequencing Requirements Clock Structure Reset Structure Thermal Interrupt Threshold Real-Time Clock BatteryReset Sequence Thermal Management Jtag Chain and Board Post Code IndicatorPost Code Indicator on the LED Debugging Support SBC Transition Module FeaturesRear Transition Module RTM Custom Debugging Functional Description Memory Map Memory Maps and RegistersPhysical Address Map Flash Memory Map Flash Memory MapLinux Devices Memory Map Memory Maps and Registers Linux Devices Memory Map PLD Revision Register Programmable Logic Device PLD RegistersPLD Revision Register PLD Year Register PLD Day Register PLD Month RegisterPLD Sequence Register Rsvd Pwrv PLD Power Good Monitor RegisterPLD Power Good Monitor Register Wrgd RGD Pwrg Oper Reset 10 PLD LED Control Register PLD LED Control RegisterPWRV1P2SWPWRG 11 PLD PCI/PMC/XMC Monitor Register PLD PCI/PMC/XMC Monitor RegisterPMC1PN 13 PLD Boot Bank Register PLD U-Boot and TSI Monitor RegisterPLD Boot Bank Register 12 PLD U-Boot and TSI Monitor Register Locka Bootb Boots Rsvd Master Flash I2CDEB Serial Wpdi WPN Ugen Flash Sabled Oper ResetPLD Write Protect and I2C Debug Register 14 PLD Write Protect and I2C Debug Register I2CDEBUGEN=0 15 PLD Test Register PLD Test Register16 PLD Test Register PLD GPIO2 Interrupt Register Rsvd NMI TICK0INT TICK1INT TICK2INT Oper Reset17 PLD GPIO2 Interrupt Register Dnmask OUT Oper Reset PLD Shutdown and Reset Control and Reset Reason Register18 PLD Shutdown and Reset Control and Reset Reason Register Cpureset Wdtime Lrsto 19 PLD Watchdog Timer Refresh Register PLD Watchdog Timer Refresh Register 20 PLD Watchdog Control Register PLD Watchdog Timer Count Register21 PLD Watchdog Timer Count Register PLD Watchdog Control Register Prescaler Register External Timer Registers22 Prescaler Register Ints Cint COC ENC Oper ResetControl Registers 23 Control Registers 24 Compare High Word Registers Compare High and Low Word Registers25 Compare Low Word Registers 26 Counter High Word Registers Counter High and Low Word Registers27 Counter Low Word Registers 102 Accessing U-Boot Boot System Booting from a Network Boot OptionsBoot System Booting from a USB Drive Booting from an Optional Sata Drive Booting VxWorks Through the Network Booting from an SD Card Analyzing Kernel Log Files after a Kernel Panic Using the Persistent Memory Feature MVME2500 Specific U-Boot Commands MVME2500 Specific U-Boot Commands Boot System Updating U-Boot Sf probe 112 POR Configuration Settings Reset ConfigurationProgramming Model Programming Model ETSEC1 TSEC1TXD0 Config Config Pins Selection Remarks ETSEC2 Sgmii LGPL1ETSEC3 Sgmmi TSEC1588ALARM Ecmdc TSEC2TXER Config Config Pins Selection Remarks Boot ROMTSEC1TXER LWE1/LBS1 MVME2500 Interrupt List Interrupt Controller PHY Types and MII Management Bus Address I2C Bus Device AddressingEthernet PHY Address I2C Bus Device Addressing TSEC3 Other Software ConsiderationsMram Quad Uart LBC Timing Parameters LBC Timing Parameters Clock Distribution Clock Distribution System Clock System Clock Local Bus Controller Clock Divisor Real Time Clock Input 124 Replacing the Battery Replacing the Battery Replacing the Battery Replacement Procedure 128 Related Documentation Emerson Network Power Embedded Computing Documents Related Documentation Related SpecificationsTable B-3 Related Specifications Manufacturers’ Documents SATA-IO PCI-SIG 132 EMC Results pending testing Safety Notes Safety Notes InstallationOperation Cabling and Connectors Battery Sicherheitshinweise Sicherheitshinweise Betrieb 139 Batterie Kabel und Stecker Umweltschutz 142 Index Index Page HOW to Reach Literature and Technical Support