Emerson MVME2500 Config Config Pins Selection Remarks Boot ROM, TSEC1TXER, LWE1/LBS1, TSEC2TXER

Programming Model

Table 7-1 POR Configuration Settings (continued)

	CONFIG	CONFIG PINS	CONFIG	SELECTION	REMARKS
24	BOOT ROM	TSEC1_TXD[6:4],	011X	On-chip boot ROM-SPI
	Location	TSEC1_TX_ER		configuration (x=0),
				SDHC (x=1)
25	Host/Agent	LWE1/LBS1,	111	The processor acts as the
	Config	LA[18:19]		host/root complex for all
				PCI-E/Serial Rapid IO
				interfaces (default).
26	I/O Port Select	TSEC1_TXD[3:1],	0010	PCI-E 1 (x1) (2.5 Gbps) -
		TSEC2_TX_ER		SerDes lane 0
				PCI-E 2 (x1) (2.5 Gbps) -
				SerDes lane 2
				PCI-E 3 (x2) (2.5 Gbps) -
				SerDes lane 2-3
27	DDR SDRAM	TSEC2_TXD1	1	DDR31.5 V. CKE low at
	TYPE			reset (default)
28	SerDes PLL Time	TRIG_OUT	1	Disable PLL lock time-out
	Out Enable			counter. The power-on-
				reset sequence waits
				indefinitely for the SerDes
				PLL to lock (default).
29	System Speed	LA[28]	1	SYSCLOCK is above 66
				MHz
30	SDHC Card	TSEC2_TXD_5	1	Not Inverted
	Detect Polarity
31	RAPID System			Default	RapidIO is not used
	Size

116 MVME2500 Installation and Use (6806800L01H)