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| 5.1 Physical Interface |
[signal] | [I/O] | [Description] |
CS0- | I | Chip select signal decoded from the host address bus. This signal |
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| is used by the host to select the command block registers. |
CS1- | I | Chip select signal decoded from the host address bus. This signal |
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| is used by the host to select the control block registers. |
DA | I | Binary decoded address signals asserted by the host to access task |
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| file registers. |
KEY | - | Key pin for prevention of erroneous connector insertion |
PDIAG- | I/O | This signal is an input mode for the master device and an output |
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| mode for the slave device in a daisy chain configuration. This |
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| signal indicates that the slave device has been completed self |
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| diagnostics. |
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| This signal is pulled up to +5 V through 10 kΩ resistor at each device. |
CBLID- | I/O | This signal is used to detect the type of cable installed in the |
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| system. |
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| This signal is pulled up to +5 V through 10 kΩ resistor at each device. |
DASP- | I/O | This is a |
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| active and a slave device is present. |
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| This signal is pulled up to +5 V through 10 kΩ resistor at each device. |
IORDY | O | This signal requests the host system to delay the transfer cycle |
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| when the device is not ready to respond to a data transfer request |
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| from the host system. |
DDMARDY- | O | Flow control signal for Ultra DMA data Out transfer (WRITE |
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| DMA command). This signal is asserted by the device to inform |
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| the host that the device is ready to receive the Ultra DMA data |
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| Out transfer. The device can negate the DDMARDY- signal to |
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| suspend the Ultra DMA data Out transfer. |
DSTROBE | O | Data In Strobe signal from the device during Ultra DMA data In |
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| transfer. Both the rising and falling edges of the DSTROBE |
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| signal latch data from Data |
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| suspend the inversion of the DSTROBE signal to suspend the |
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| Ultra DMA data In transfer. |
CSEL | I | This signal to configure the device as a master or a slave device. |
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| − When CSEL signal is grounded, the IDD is a master device. |
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| − When CSEL signal is open, the IDD is a slave device. |
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| This signal is pulled up with 240 kΩ resistor at each device. |
DMACK- | I | The host system asserts this signal as a response that the host |
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| system receive data or to indicate that data is valid. |