Interface
5.3.2 Command descriptions
The contents of the I/O registers to be necessary for issuing a command and the example indication of the I/O registers at command completion are shown as following in this subsection.
Example: READ SECTOR(S)
At command issuance (I/O registers setting contents) |
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Bit | 7 |
| 6 | 5 | 4 | 3 |
| 2 | 1 |
| 0 |
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1F7H(CM) | 0 |
| 0 | 1 | 0 | 0 |
| 0 | 0 |
| 0 |
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1F6H(DH) | x |
| L | x | DV | Head No. / LBA [MSB] | |||||
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1F5H(CH) | Start cylinder address [MSB] / LBA |
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1F4H(CL) | Start cylinder address [LSB] / LBA |
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1F3H(SN) | Start sector No. / LBA [LSB] |
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1F2H(SC) | Transfer sector count |
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1F1H(FR) | xx |
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At command completion (I/O registers contents to be read) |
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Bit | 7 |
| 6 | 5 | 4 | 3 |
| 2 | 1 |
| 0 |
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1F7H(ST) | Status information |
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1F6H(DH) | x |
| L | x | DV | Head No. / LBA [MSB] | |||||
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1F5H(CH) | End cylinder address [MSB] / LBA |
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1F4H(CL) | End cylinder address [LSB] / LBA |
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1F3H(SN) | End sector No. / LBA [LSB] |
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1F2H(SC) | X’00’ |
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1F1H(ER) | Error information |
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CM: Command register | FR: Features register |
DH: Device/Head register | ST: Status register |
CH: Cylinder High register | ER: Error register |
CL: Cylinder Low register | L: LBA (logical block address) setting bit |
SN: Sector Number register | DV: Device address. bit |
