At command completion (I/O registers contents to be read)
1F7H(ST) |
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| Status information |
| ||
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|
|
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|
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1F6H(DH) | × | × | × |
| DV |
| xx |
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|
|
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1F5H(CH) |
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| xx |
| |
1F4H(CL) |
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|
| xx |
| |
1F3H(SN) |
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|
| xx |
| |
1F2H(SC) |
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|
|
| xx |
| |
1F1H(ER) |
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| Error information |
| ||
(23)IDLE IMMEDIATE (X'95' or X'E1')
Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. This command does not support the automatic
At command issuance (I/O registers setting contents)
1F7H(CM) |
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| X'95' or X'E1' |
| |
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|
1F6H(DH) | × | × | × | DV |
| xx |
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|
|
|
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1F5H(CH) |
|
|
| xx |
| |
1F4H(CL) |
|
|
| xx |
| |
1F3H(SN) |
|
|
| xx |
| |
1F2H(SC) |
|
|
| xx |
| |
1F1H(FR) |
|
|
| xx |
| |
At command completion (I/O registers contents to be read)
1F7H(ST) |
|
|
| Status information |
| ||
|
|
|
|
|
|
|
|
1F6H(DH) | × | × | × |
| DV |
| xx |
|
|
|
|
|
|
|
|
1F5H(CH) |
|
|
|
| xx |
| |
1F4H(CL) |
|
|
|
| xx |
| |
1F3H(SN) |
|
|
|
| xx |
| |
1F2H(SC) |
|
|
|
| xx |
| |
1F1H(ER) |
|
|
| Error information |
| ||
| 5 - 45 |
