Table 5.20 Ultra DMA sender and recipient timing requirements
| MODE 0 | MODE 1 | MODE 2 | MODE 3 | MODE 4 | MODE 5 |
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NAME | (in ns) | (in ns) | (in ns) | (in ns) | (in ns) | (in ns) | COMMENT | ||||||
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| MIN | MAX | MIN | MAX | MIN | MAX | MIN | MAX | MIN | MAX | MIN | MAX |
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tDSIC | 14.7 |
| 9.7 |
| 6.8 |
| 6.8 |
| 4.8 |
| 2.3 |
| Recipient IC data setup time (from |
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| data valid until STROBE edge) |
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tDHIC | 4.8 |
| 4.8 |
| 4.8 |
| 4.8 |
| 4.8 |
| 2.8 |
| Recipient IC data hold time (from |
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| STROBE edge until data may |
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| become invalid) (*1) |
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tDVSIC | 72.9 |
| 50.9 |
| 33.9 |
| 22.6 |
| 9.5 |
| 6 |
| Sender IC data valid setup time |
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| (from data valid until STROBE |
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| edge) (*2) |
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tDVHIC | 9 |
| 9 |
| 9 |
| 9 |
| 9 |
| 6 |
| Sender IC data valid hold time |
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| (from STROBE edge until data |
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| may become invalid) (*2) |
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*1: The correct data value shall be captured by the recipient given input data with a slew rate of 0.4 V/ns rising and falling and the input STROBE with a slew rate of 0.4 V/ns rising and falling at tDSIC and tDHIC timing (as measured through 1.5V).
*2: The parameters tDVSIC and tDVHIC shall be met for lumped capacitive loads of 15 and 40 pf at the IC where all signals have the same capacitive load value. Noise that may couple onto the output signals from external sources in a normally functioning system has not
been included in these values.
Note:
All timing measurement switching points (low to high and high to low) shall be taken at 1.5V.
5 - 100 |
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