[signal] | [I/O] | [Description] |
IORDY | O | This signal is negated to extend the host transfer cycle of any host register |
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| access (Read or Write) when the device is not ready to respond to a data |
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| transfer request. |
DDMARDY– | O | DDMARDY– is a flow control signal for Ultra DMA data out bursts. |
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| This signal is asserted by the device to indicate to the host that the device |
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| is ready to receive Ultra DMA data out bursts. The device may negate |
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| DDMARDY– to pause an Ultra DMA data out burst. |
DSTROBE | O | DSTROBE is the data in strobe signal from the device for an Ultra |
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| DMA data in burst. Both the rising and falling edge of DSTROBE |
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| latch the data from DATA |
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| generating DSTROBE edges to pause an Ultra DMA data in burst. |
CSEL | I | This signal to configure the device as a master or a slave device. |
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| When CSEL signal is grounded, the IDD is a master device. |
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| When CSEL signal is open, the IDD is a slave device. |
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| This signal is pulled up with 10 kΩ resistor. |
DMACK– | I | The host system asserts this signal as a response that the host system |
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| receive data or to indicate that data is valid. |
DMARQ | O | This signal is used for DMA transfer between the host system and the |
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| device. The device asserts this signal when the device completes the |
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| preparation of DMA data transfer to the host system (at reading) or |
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| from the host system (at writing). |
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| The direction of data transfer is controlled by the IOR- and IOW- |
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| signals. In other word, the device negates the DMARQ signal after |
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| the host system asserts the DMACK– signal. When there is another |
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| data to be transferred, the device asserts the DMARQ signal again. |
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| When the DMA data transfer is performed, |
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| CS1- signals are not asserted. The DMA data transfer is a |
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| transfer. The device has a 10 kΩ |
GND | – | Grounded |
Note:
"I" indicates input signal from the host to the device. "O" indicates output signal from the device to the host.
"I/O" indicates common output or
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