EM78P312N
Bit 3 (P): Power down bit. Set to “1” during power on or by a "WDTC" command and reset to “0” by a "SLEP" command.
Bit 2 (Z): Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 1 (DC) : Auxiliary carry flag
Bit 0 (C) : Carry flag
R4 (RAM Select Register)
Bit 7 | Bit 6 | Bit 5 | Bit 4 |
Bit 3
Bit 2 | Bit 1 | Bit 0 |
GRBS1
RBS0
RSR5
RSR4
RSR3
RSR2
RSR1
RSR0
Bit 7: 6 ( GRBS1: GRBS0 ): determine which general purpose banks are activated among the two banks. Use BANK instruction (e.g. BABK 1) to change bank.
GRBS1 |
| GRBS0 |
| General Purpose Register Bank (Address 20H ~ 3FH) |
0 |
| 0 |
| Bank 0 |
0 |
| 1 |
| Bank 1 |
Bit 5: 0 ( RSR5 : RSR0 ): used to select the registers (Address: 00h~3Fh) in indirect addressing mode. If no indirect addressing is used, the RSR can be used as an
R5 (System Control Register)
Bit 7 | Bit 6 | Bit 5 | Bit 4 | |
Bit 3
Bit 2 | Bit 1 | Bit 0 | |
0
0
PS1
PS0
0
1
SIS
REM
Bits 5~4 (PS1~PS0): ROM Page select bits. User can use PAGE instruction (e.g. PAGE 1) or set PS1~PS0 bits to change the ROM page. When executing a "JMP", "CALL", or other instructions which cause the program counter to change (e.g. MOV R2, A), PS1~PS0 are loaded into the 12th to11th bits of the program counter and select one of the available program memory pages. Note that RET (RETL, RETI) instruction does not change the PS1~PS0 bits. That is, return will always be to the page from where the subroutine was called, regardless of the PS1~PS0 bits current setting.
PS1 |
| PS0 |
| Program Memory Page [Address] |
0 |
| 0 |
| Page 0 [0000~03FF] |
0 |
| 1 |
| Page 1 [0400~07FF] |
1 |
| 0 |
| Page 2 [0800~0BFF] |
1 |
| 1 |
| Page 3 [0C00~0FFF] |
Bit 1 ( SIS ) : Sleep and Idle mode select
SIS = “0” : Idle mode
SIS = “1” : Sleep mode
Bit 0 ( REM ) : Release method for sleep mode
REM = “0” : /SLEEP pin input rising edge released
REM = “1” : /SLEEP pin input “H” level released
Product Specification (V1.0) 10.03.2006 | • 7 |
(This specification is subject to change without further notice)
