Bit 0 C Carry flag R4 RAM Select Register | IBM EM78P312N instruction

EM78P312N

8-Bit Microcontroller

Bit 3 (P): Power down bit. Set to “1” during power on or by a "WDTC" command and reset to “0” by a "SLEP" command.

Bit 2 (Z): Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero.

Bit 1 (DC) : Auxiliary carry flag

Bit 0 (C) : Carry flag

R4 (RAM Select Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

GRBS1

RBS0

RSR5

RSR4

RSR3

RSR2

RSR1

RSR0

Bit 7: 6 ( GRBS1: GRBS0 ): determine which general purpose banks are activated among the two banks. Use BANK instruction (e.g. BABK 1) to change bank.

GRBS1		GRBS0		General Purpose Register Bank (Address 20H ~ 3FH)
0		0		Bank 0
0		1		Bank 1

Bit 5: 0 ( RSR5 : RSR0 ): used to select the registers (Address: 00h~3Fh) in indirect addressing mode. If no indirect addressing is used, the RSR can be used as an 8-bit general-purpose read/write register. See the data memory configuration in Fig. 5-2.

R5 (System Control Register)

	Bit 7	Bit 6	Bit 5	Bit 4

Bit 3

	Bit 2	Bit 1	Bit 0

0

0

PS1

PS0

0

1

SIS

REM

Bits 5~4 (PS1~PS0): ROM Page select bits. User can use PAGE instruction (e.g. PAGE 1) or set PS1~PS0 bits to change the ROM page. When executing a "JMP", "CALL", or other instructions which cause the program counter to change (e.g. MOV R2, A), PS1~PS0 are loaded into the 12th to11th bits of the program counter and select one of the available program memory pages. Note that RET (RETL, RETI) instruction does not change the PS1~PS0 bits. That is, return will always be to the page from where the subroutine was called, regardless of the PS1~PS0 bits current setting.

PS1		PS0		Program Memory Page [Address]
0		0		Page 0 [0000~03FF]
0		1		Page 1 [0400~07FF]
1		0		Page 2 [0800~0BFF]
1		1		Page 3 [0C00~0FFF]

Bit 1 ( SIS ) : Sleep and Idle mode select

SIS = “0” : Idle mode

SIS = “1” : Sleep mode

Bit 0 ( REM ) : Release method for sleep mode

REM = “0” : /SLEEP pin input rising edge released

REM = “1” : /SLEEP pin input “H” level released

Product Specification (V1.0) 10.03.2006

• 7

(This specification is subject to change without further notice)

Image 11

IBM EM78P312N Bit 0 C Carry flag R4 RAM Select Register, R5 System Control Register, Bit 1 SIS Sleep and Idle mode select

Contents

DOC. Version EM78P312N Elan Microelectronics Corporation Contents 16.3 14.116.1 16.2 Bit Microcontroller General Description Pin Description Symbol Pin No Type Function Function Description Functional Block Diagram Operating Registers Operating Registers R2 Program Counter & Stack Bit Microcontroller R0 Indirect Addressing RegisterR1 Time Clock /Counter RBS1 RBS0 User Memory SpaceR3 Status Register Bit 7 ~ Bit 6 RBS1 ~ RBS0 R-Register page select R5 System Control Register Bit 1 SIS Sleep and Idle mode selectSIS = 0 Idle mode SIS = 1 Sleep mode Bit 0 C Carry flag R4 RAM Select Register R7 Port 7 I/O Data Register RB Timer/Counter 4 Control RegisterBit Microcontroller R6 Port 6 I/O Data Register Bit 7 ~ Bit 0 P67 ~ P60 8-bit Port 6 I/O data register Fosc=8M RC Timer 4 Data BufferClock Source Resolution Max. Time TC4CK2 TC4CK1 TC4CK0 RFInterrupt Status Flag Register Bit Microcontroller RE Interrupt Status Flag Register Bit 7 TC3CAP Software capture control Bank 1 R5 TC3CR Timer/Counter 3 Control RegisterTC3M = 1 Capture mode Bank 1 R6 TC3DA Timer 3 Data Buffer a Bank 1 R7 TC3DB Timer 3 Data Buffer B Bank 1 RB Adcr AD Control Register Bank 1 R9 TC2DH Timer 2 Data Buffer High ByteBank 1 RA TC2DL Timer 2 Data Buffer Low Byte TC2S = 0 Stop and counter clear Bank 1 RD Addh AD High 8-bit Data Buffer Bit 7 ~ Bit 0 ADE7 ~ ADE0 AD input pin enable controlBit 5~ Bit 4 ADCK1 ~ ADCK0 AD Conversion Time Select Bank 1 RC Adic AD Input Pin Control Bit TEN = 0 Disable TEN = 1 EnableBit Microcontroller Bank 1 RE Tbktc TBT/Keytone Control Bank 2 R5 URC1 Uart Control Register TC2CK1 TC2CK0 Bank 2 R7 URS Uart Status RegisterBit 7 URRD8 Receiving data Bit BRATE2 BRATE1 BRATE0 Bank 2 R9 Urtd Uart Transmit Data Buffer Bit 5 PRE Enable parity additionBit 6 Even Select parity check Even = 0 Odd parity Even = 1 Even parity Bit 0 WBE Write buffer empty flag. Read only Bit 5 ~ Bit 3 BRS0 ~ BRS2 SPI Clock Source SelectBit 2 EDS Data shift out edge select EDS = 0 Rising edge EDS = 1 Falling edge SPID7 SPID6 SPID5 SPID4 SPID3 SPID2 SPID1 SPID0 PHE6x = 1 Disable P6x pull highTransfer Mode Bank 3 RB PLC1 Pull Low Control Register Special Purpose Registers TC2ES = 0 Rising edge TC2ES = 1 Falling edge IOC6 ~ IOC9 − I/O Port Control RegisterIntcr − INT Control Register Address 0Bh INT1ES = 0 Rising edge INT1ES = 1 Falling edge Cali Sign External InterruptAdoscr − AD Offset Control Register Address 0Ch Uerrie Urie Utie Tbie EXIE1 TCIE0 IMR2 − Interrupt Mask Register 2 Address 0Fh Operation Mode CPU Operation ModeRegisters for CPU Operation Mode Mode Switching Control Wake-up Methods Sleep Mode Idle ModeWake-up Signal R5 SIS = 1+SLEP R5 SIS= 0 + Slep Instruction AD Converter Conversion Time Operation Mode Max. Frequency Max. Conversion Rate per BitADC Data Register Sampling Time Address Name Bit Time Base Timer and Keytone Generator MUX Name Bit Uart Universal Asynchronous Receiver/TransmitterRegisters for Uart Circuit Transmitting Uart Mode Baud Rate Generator Receiving Rbank Address Name Bit SPI Serial Peripheral InterfaceRegisters for the SPI Circuit Serial Clock Shift Direction and Sample PhaseTransfer Mode Bit Transmit Mode SCK pin Bit Microcontroller Bit Receive ModeBit Transmit/Receive Mode Multiple Device Connect /SS Spis Registers for Timer/Counter 2 Circuit Timer/Counter Window Mode Timer ModeCounter Mode 21 Window Mode Timing Chart Registers for Timer/Counter 3 Circuit 22 Configuration of Timer/Counter3 Capture Mode TCIF4 Registers for Timer 4 Circuit TCR4 PDO Mode TC4 Interrupt PWM Mode12 TCC/WDT & Prescaler Up-counter 13 I/O Ports Reset and Wake-upReset Wake-up from Idle Mode Wake-up from Sleep Mode Summary of the Initialized Values for Registers Address Name Reset Type Bit SCR Bit Microcontroller Register Bank Addres URTD8 Events that may affect the T and P Status Reset TypeStatus of RST, T, and P of the Status Register Bit Microcontroller General Purpose Registers Interrupt 28 Controller Reset Block Diagram Summary of Maximum Operating Speeds OscillatorOscillator Modes Crystal Oscillator/Ceramic Resonators Crystal 740 EM78P312N 809N Oscillator Type Frequency Mode Frequency C1 pF C2 pF OS CI External RC Oscillator Mode Bit 12 ~ 9 Not used Enwdtb = 0 Enable Enwdtb = 1 DisableCode Option Register Code Option Register Word OSC = 0 RC type OSC = 1 Crystal type Power-on ConsiderationsExternal Power-on Reset Circuit Customer ID Register EM78P809N Residue-Voltage ProtectionVdd EM78P312N Binary Instruction Hex Mnemonic Operation Status Instruction Set DEC Binary Instruction Hex Mnemonic Operation Status Affected Vss = Symbol Parameter Condition Min Typ Max UnitAbsolute Maximum Ratings Recommended Operating Conditions Ta= 25 C, VDD= 5.0V ± 5%, VSS= DC Electrical Characteristics Ta= 25 C, VDD= 3.0V ± 5%, VSS= Varef Ta=- 40C ~ 85 C, VDD=5V ± 5%, VSS=0V AC Electrical CharacteristicSymbol Parameter Conditions Min Typ Max Unit AC Test Input/Output Waveform Timing Diagram EM78P311SxY OTP MCUPackage Type Pin Count Package Size