EM78P312N
8-Bit Microcontroller
Register Bank 1
Addres |
| Name | Reset Type |
| Bit 7 |
| Bit 6 |
| Bit 5 |
| Bit 4 |
| Bit 3 |
| Bit 2 |
| Bit 1 |
| Bit 0 |
s |
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| Bit Name |
| TC3CAP |
| TC3S |
| TC3CK1 |
| TC3CK0 |
| TC3M |
| X |
| X |
| X |
0x05 |
| TC3CR |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| U |
| U |
| U | |
| /RESET and WDT time out |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| U |
| U |
| U | ||
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| P |
| P |
| P |
| P |
| P |
| U |
| U |
| U | |
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| Bit Name |
| TC3DA7 |
| TC3DA6 |
| TC3DA5 |
| TC3DA4 |
| TC3DA3 |
| TC3DA2 |
| TC3DA1 |
| TC3DA0 |
0x06 |
| TC3DA |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 | |
| /RESET and WDT time out |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 | ||
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| P |
| P |
| P |
| P |
| P |
| P |
| P |
| P | |
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| Bit Name |
| TC3DB7 |
| TC3DB6 |
| TC3DB5 |
| TC3DB4 |
| TC3DB3 |
| TC3DB2 |
| TC3DB1 |
| TC3DB0 |
0x07 |
| TC3DB |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 | |
| /RESET and WDT time out |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 | ||
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| P |
| P |
| P |
| P |
| P |
| P |
| P |
| P | |
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| Bit Name |
| ADD1 |
| ADD0 |
| X |
| TC2M |
| TC2S |
| TC2CK2 |
| TC2CK1 |
| TC2CK0 |
0x08 |
| TC2CR/ |
| U |
| U |
| U |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 | |
| ADDL | /RESET and WDT time out |
| P |
| P |
| U |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 | |
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| P |
| P |
| U |
| P |
| 0 |
| P |
| P |
| P | |
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| Bit Name |
| TC2D15 |
| TC2D14 |
| TC2D13 |
| TC2D12 |
| TC2D11 |
| TC2D10 |
| TC2D9 |
| TC2D8 |
0x09 |
| TC2DH |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 | |
| /RESET and WDT time out |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 | ||
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| P |
| P |
| P |
| P |
| P |
| P |
| P |
| P | |
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| Bit Name |
| TC2D7 |
| TC2D6 |
| TC2D5 |
| TC2D4 |
| TC2D3 |
| TC2D2 |
| TC2D1 |
| TC2D0 |
0x0A |
| TC2DL |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 | |
| /RESET and WDT time out |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 | ||
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| P |
| P |
| P |
| P |
| P |
| P |
| P |
| P | |
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| Bit Name |
| ADREF |
| ADRUN |
| ADCK1 |
| ADCK0 |
| ADP |
| ADIS2 |
| ADIS1 |
| ADIS0 |
0x0B |
| ADCR |
| 0 |
| 0 |
| 0 |
| 0 |
| 1 |
| 0 |
| 0 |
| 0 | |
| /RESET and WDT time out |
| 0 |
| 0 |
| 0 |
| 0 |
| 1 |
| 0 |
| 0 |
| 0 | ||
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| P |
| (*) |
| P |
| P |
| P |
| P |
| P |
| P | |
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| Bit Name |
| ADE7 |
| ADE6 |
| ADE5 |
| ADE4 |
| ADE3 |
| ADE2 |
| ADE1 |
| ADE0 |
0x0C |
| ADIC |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 | |
| /RESET and WDT time out |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 | ||
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| P |
| P |
| P |
| P |
| P |
| P |
| P |
| P | |
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| Bit Name |
| ADD9 |
| ADD8 |
| ADD7 |
| ADD6 |
| ADD5 |
| ADD4 |
| ADD3 |
| ADD2 |
0X0D |
| ADDH |
| U |
| U |
| U |
| U |
| U |
| U |
| U |
| U | |
| /RESET and WDT time out |
| P |
| P |
| P |
| P |
| P |
| P |
| P |
| P | ||
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| P |
| P |
| P |
| P |
| P |
| P |
| P |
| P | |
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| Bit Name |
| TEN |
| TCK1 |
| TCK0 |
| X |
| TBTEN |
| TBTCK2 |
| TBTCK1 |
| TBTCK0 |
0X0E |
| TBKTC |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 | |
| /RESET and WDT time out |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 |
| 0 | ||
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| 0 |
| P |
| P |
| P |
| 0 |
| P |
| P |
| P |
46 • | Product Specification (V1.0) 10.03.2006 |
(This specification is subject to change without further notice)