Spis, Multiple Device Connect /SS | IBM EM78P312N specs

EM78P312N

8-Bit Microcontroller

	shift start		shift start
SPIS
RBF	shift finish
WBE	shift finish
/SCK pin
SO pin	a0 a1 a2 a3 a4 a5 a6 a7		b0 b1 b2 b3 b4 b5 b6 b7
SI pin	c0 c1 c2 c3 c4 c5 c6 c7		d0 d1 d2 d3 d4 d5 d6 d7
SPIF
SPID	a	c	b	d
	write data	read data	write data	read data
	Fig. 5-16 Transmit/Receive Mode (8-bit, 1 word)

(d) Multiple Device Connect (/SS)

When selecting external clock for transfer clock source, the /SS function can be used. This pin (/SS) will be active when the /SS function is enabled, else the /SS pin is a general purpose I/O. Ignore the data on the SDI and SDO pins while /SS is high, since the SDO is no longer driven.

		SDO
		SDI
		SCK
		/SS
Master		P67
Master		P66
		P65
		P64
/SS	SDO	/SS	SDO	/SS	SDO	/SS	SDO
SCK	SDI	SCK	SDI	SCK	SDI	SCK	SDI
Slave Device 1		Slave Device 2		Slave Device 3		Slave Device 4

Fig. 5-17 The SPI Configuration Example of Single-Master and Multi-Slaves

34 •	Product Specification (V1.0) 10.03.2006

(This specification is subject to change without further notice)

Image 38

IBM EM78P312N manual Spis, Multiple Device Connect /SS

Contents

EM78P312N DOC. Version Elan Microelectronics Corporation Contents 16.2 14.116.1 16.3 General Description Bit Microcontroller Symbol Pin No Type Function Pin Description Functional Block Diagram Function Description Operating Registers Operating Registers R2 Program Counter & Stack Bit Microcontroller R0 Indirect Addressing RegisterR1 Time Clock /Counter Bit 7 ~ Bit 6 RBS1 ~ RBS0 R-Register page select User Memory SpaceR3 Status Register RBS1 RBS0 Bit 0 C Carry flag R4 RAM Select Register Bit 1 SIS Sleep and Idle mode selectSIS = 0 Idle mode SIS = 1 Sleep mode R5 System Control Register Bit 7 ~ Bit 0 P67 ~ P60 8-bit Port 6 I/O data register RB Timer/Counter 4 Control RegisterBit Microcontroller R6 Port 6 I/O Data Register R7 Port 7 I/O Data Register TC4CK2 TC4CK1 TC4CK0 RC Timer 4 Data BufferClock Source Resolution Max. Time Fosc=8M Bit Microcontroller RE Interrupt Status Flag Register RFInterrupt Status Flag Register Bank 1 R7 TC3DB Timer 3 Data Buffer B Bank 1 R5 TC3CR Timer/Counter 3 Control RegisterTC3M = 1 Capture mode Bank 1 R6 TC3DA Timer 3 Data Buffer a Bit 7 TC3CAP Software capture control TC2S = 0 Stop and counter clear Bank 1 R9 TC2DH Timer 2 Data Buffer High ByteBank 1 RA TC2DL Timer 2 Data Buffer Low Byte Bank 1 RB Adcr AD Control Register Bank 1 RC Adic AD Input Pin Control Bit 7 ~ Bit 0 ADE7 ~ ADE0 AD input pin enable controlBit 5~ Bit 4 ADCK1 ~ ADCK0 AD Conversion Time Select Bank 1 RD Addh AD High 8-bit Data Buffer Bank 2 R5 URC1 Uart Control Register TEN = 0 Disable TEN = 1 EnableBit Microcontroller Bank 1 RE Tbktc TBT/Keytone Control Bit BRATE2 BRATE1 BRATE0 Bank 2 R7 URS Uart Status RegisterBit 7 URRD8 Receiving data Bit TC2CK1 TC2CK0 Even = 0 Odd parity Even = 1 Even parity Bit 5 PRE Enable parity additionBit 6 Even Select parity check Bank 2 R9 Urtd Uart Transmit Data Buffer EDS = 0 Rising edge EDS = 1 Falling edge Bit 5 ~ Bit 3 BRS0 ~ BRS2 SPI Clock Source SelectBit 2 EDS Data shift out edge select Bit 0 WBE Write buffer empty flag. Read only Bank 3 RB PLC1 Pull Low Control Register PHE6x = 1 Disable P6x pull highTransfer Mode SPID7 SPID6 SPID5 SPID4 SPID3 SPID2 SPID1 SPID0 Special Purpose Registers INT1ES = 0 Rising edge INT1ES = 1 Falling edge IOC6 ~ IOC9 − I/O Port Control RegisterIntcr − INT Control Register Address 0Bh TC2ES = 0 Rising edge TC2ES = 1 Falling edge Cali Sign External InterruptAdoscr − AD Offset Control Register Address 0Ch IMR2 − Interrupt Mask Register 2 Address 0Fh Uerrie Urie Utie Tbie EXIE1 TCIE0 Mode Switching Control CPU Operation ModeRegisters for CPU Operation Mode Operation Mode AD Converter Sleep Mode Idle ModeWake-up Signal R5 SIS = 1+SLEP R5 SIS= 0 + Slep Instruction Wake-up Methods Sampling Time Operation Mode Max. Frequency Max. Conversion Rate per BitADC Data Register Conversion Time Time Base Timer and Keytone Generator Address Name Bit MUX Name Bit Uart Universal Asynchronous Receiver/TransmitterRegisters for Uart Circuit Uart Mode Transmitting Receiving Baud Rate Generator Rbank Address Name Bit SPI Serial Peripheral InterfaceRegisters for the SPI Circuit Bit Transmit Mode Shift Direction and Sample PhaseTransfer Mode Serial Clock SCK pin Bit Microcontroller Bit Receive ModeBit Transmit/Receive Mode Spis Multiple Device Connect /SS Timer/Counter Registers for Timer/Counter 2 Circuit Window Mode Timer ModeCounter Mode Registers for Timer/Counter 3 Circuit 21 Window Mode Timing Chart Capture Mode 22 Configuration of Timer/Counter3 Registers for Timer 4 Circuit TCIF4 PDO Mode TCR4 Up-counter PWM Mode12 TCC/WDT & Prescaler TC4 Interrupt 13 I/O Ports Reset and Wake-upReset Wake-up from Sleep Mode Wake-up from Idle Mode Address Name Reset Type Bit Summary of the Initialized Values for Registers Bit Microcontroller Register Bank SCR Addres URTD8 Bit Microcontroller General Purpose Registers Reset TypeStatus of RST, T, and P of the Status Register Events that may affect the T and P Status 28 Controller Reset Block Diagram Interrupt Crystal Oscillator/Ceramic Resonators Crystal OscillatorOscillator Modes Summary of Maximum Operating Speeds Oscillator Type Frequency Mode Frequency C1 pF C2 pF 740 EM78P312N 809N External RC Oscillator Mode OS CI Code Option Register Word Enwdtb = 0 Enable Enwdtb = 1 DisableCode Option Register Bit 12 ~ 9 Not used Customer ID Register Power-on ConsiderationsExternal Power-on Reset Circuit OSC = 0 RC type OSC = 1 Crystal type EM78P312N Residue-Voltage ProtectionVdd EM78P809N Instruction Set Binary Instruction Hex Mnemonic Operation Status Binary Instruction Hex Mnemonic Operation Status Affected DEC Recommended Operating Conditions Symbol Parameter Condition Min Typ Max UnitAbsolute Maximum Ratings Vss = DC Electrical Characteristics Ta= 25 C, VDD= 5.0V ± 5%, VSS= Ta= 25 C, VDD= 3.0V ± 5%, VSS= Varef Ta=- 40C ~ 85 C, VDD=5V ± 5%, VSS=0V AC Electrical CharacteristicSymbol Parameter Conditions Min Typ Max Unit Timing Diagram AC Test Input/Output Waveform Pin Count Package Size OTP MCUPackage Type EM78P311SxY