Bit 6 Even Select parity check | IBM EM78P312N manual

EM78P312N

8-Bit Microcontroller

Bit 6 ( EVEN ) : Select parity check

EVEN = “0” : Odd parity

EVEN = “1” : Even parity

Bit 5 ( PRE ) : Enable parity addition

PRE = “0” : Disable

PRE = “1” : Enable

Bit 4 ( PRERR ) : Parity error flag.

Set to 1 when parity error occurred, and cleared to 0 by software.

Bit 3 ( OVERR ) : Overrun error flag.

Set to 1 when overrun error occurred, and cleared to 0 by software.

Bit 2 ( FMERR ) : Framing error flag.

Set to 1 when framing error occurred, and cleared to 0 by software.

Bit 1 ( URBF ) : UART read buffer full flag.

Set to 1 when one character is received. Reset to 0 automatically when read from the URS register. URBF will be cleared by hardware when receiving is enabled. URBF bit is read-only. Therefore, reading the URS register is necessary to avoid an overrun error.

Bit 0 ( RXE ) : Enable receiving

RXE = “0” : Disable

RXE = “1” : Enable

Bank 2 R8 URRD (UART Receive Data Buffer)

Bit 7		Bit 6		Bit 5		Bit 4	Bit 3	Bit 2	Bit 1	Bit 0

URRD7		URRD6		URRD5		URRD4	URRD3	URRD2	URRD1	URRD0

Bit 7 ~ Bit 0 ( URRD7 ~ URRD0 ) : UART receive data buffer. Read only.

Bank 2 R9 URTD (UART Transmit Data Buffer)

	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0

URTD 7 URTD 6 URTD 5 URTD 4 URTD 3

URTD 2 URTD 1

URTD0

Bit 7 ~ Bit 0 ( URTD 7 ~ URTD 0) : UART transmit data buffer. Write only.

Bank 3 R5 SPIC1 (SPI Control Register 1)

Bit 7		Bit 6		Bit 5		Bit 4
SMP		DCOL		BRS2		BRS1

Bit 3

BRS0

	Bit 2	Bit 1		Bit 0
	EDS	DORD		WBE

Bit 7 ( SMP ) : SPI data input sample phase.

SMP = “0” : Input data sampled at middle of data output time

SMP = “1” : Input data sampled at the end of data output time

16 •	Product Specification (V1.0) 10.03.2006

(This specification is subject to change without further notice)

Image 20

IBM EM78P312N Bit 6 Even Select parity check, Even = 0 Odd parity Even = 1 Even parity, Bit 5 PRE Enable parity addition

Contents

EM78P312N DOC. Version Elan Microelectronics Corporation Contents 14.1 16.116.2 16.3 General Description Bit Microcontroller Symbol Pin No Type Function Pin Description Functional Block Diagram Function Description Operating Registers Operating Registers R2 Program Counter & Stack Bit Microcontroller R0 Indirect Addressing RegisterR1 Time Clock /Counter User Memory Space R3 Status RegisterBit 7 ~ Bit 6 RBS1 ~ RBS0 R-Register page select RBS1 RBS0 Bit 1 SIS Sleep and Idle mode select SIS = 0 Idle mode SIS = 1 Sleep modeBit 0 C Carry flag R4 RAM Select Register R5 System Control Register RB Timer/Counter 4 Control Register Bit Microcontroller R6 Port 6 I/O Data RegisterBit 7 ~ Bit 0 P67 ~ P60 8-bit Port 6 I/O data register R7 Port 7 I/O Data Register RC Timer 4 Data Buffer Clock Source Resolution Max. TimeTC4CK2 TC4CK1 TC4CK0 Fosc=8M Bit Microcontroller RE Interrupt Status Flag Register RFInterrupt Status Flag Register Bank 1 R5 TC3CR Timer/Counter 3 Control Register TC3M = 1 Capture mode Bank 1 R6 TC3DA Timer 3 Data Buffer aBank 1 R7 TC3DB Timer 3 Data Buffer B Bit 7 TC3CAP Software capture control Bank 1 R9 TC2DH Timer 2 Data Buffer High Byte Bank 1 RA TC2DL Timer 2 Data Buffer Low ByteTC2S = 0 Stop and counter clear Bank 1 RB Adcr AD Control Register Bit 7 ~ Bit 0 ADE7 ~ ADE0 AD input pin enable control Bit 5~ Bit 4 ADCK1 ~ ADCK0 AD Conversion Time SelectBank 1 RC Adic AD Input Pin Control Bank 1 RD Addh AD High 8-bit Data Buffer TEN = 0 Disable TEN = 1 Enable Bit Microcontroller Bank 1 RE Tbktc TBT/Keytone ControlBank 2 R5 URC1 Uart Control Register Bit Bank 2 R7 URS Uart Status Register Bit 7 URRD8 Receiving data BitBRATE2 BRATE1 BRATE0 TC2CK1 TC2CK0 Bit 5 PRE Enable parity addition Bit 6 Even Select parity checkEven = 0 Odd parity Even = 1 Even parity Bank 2 R9 Urtd Uart Transmit Data Buffer Bit 5 ~ Bit 3 BRS0 ~ BRS2 SPI Clock Source Select Bit 2 EDS Data shift out edge selectEDS = 0 Rising edge EDS = 1 Falling edge Bit 0 WBE Write buffer empty flag. Read only PHE6x = 1 Disable P6x pull high Transfer ModeBank 3 RB PLC1 Pull Low Control Register SPID7 SPID6 SPID5 SPID4 SPID3 SPID2 SPID1 SPID0 Special Purpose Registers IOC6 ~ IOC9 − I/O Port Control Register Intcr − INT Control Register Address 0BhINT1ES = 0 Rising edge INT1ES = 1 Falling edge TC2ES = 0 Rising edge TC2ES = 1 Falling edge Cali Sign External InterruptAdoscr − AD Offset Control Register Address 0Ch IMR2 − Interrupt Mask Register 2 Address 0Fh Uerrie Urie Utie Tbie EXIE1 TCIE0 CPU Operation Mode Registers for CPU Operation ModeMode Switching Control Operation Mode Sleep Mode Idle Mode Wake-up Signal R5 SIS = 1+SLEP R5 SIS= 0 + Slep InstructionAD Converter Wake-up Methods Operation Mode Max. Frequency Max. Conversion Rate per Bit ADC Data RegisterSampling Time Conversion Time Time Base Timer and Keytone Generator Address Name Bit MUX Name Bit Uart Universal Asynchronous Receiver/TransmitterRegisters for Uart Circuit Uart Mode Transmitting Receiving Baud Rate Generator Rbank Address Name Bit SPI Serial Peripheral InterfaceRegisters for the SPI Circuit Shift Direction and Sample Phase Transfer ModeBit Transmit Mode Serial Clock SCK pin Bit Microcontroller Bit Receive ModeBit Transmit/Receive Mode Spis Multiple Device Connect /SS Timer/Counter Registers for Timer/Counter 2 Circuit Window Mode Timer ModeCounter Mode Registers for Timer/Counter 3 Circuit 21 Window Mode Timing Chart Capture Mode 22 Configuration of Timer/Counter3 Registers for Timer 4 Circuit TCIF4 PDO Mode TCR4 PWM Mode 12 TCC/WDT & PrescalerUp-counter TC4 Interrupt 13 I/O Ports Reset and Wake-upReset Wake-up from Sleep Mode Wake-up from Idle Mode Address Name Reset Type Bit Summary of the Initialized Values for Registers Bit Microcontroller Register Bank SCR Addres URTD8 Reset Type Status of RST, T, and P of the Status RegisterBit Microcontroller General Purpose Registers Events that may affect the T and P Status 28 Controller Reset Block Diagram Interrupt Oscillator Oscillator ModesCrystal Oscillator/Ceramic Resonators Crystal Summary of Maximum Operating Speeds Oscillator Type Frequency Mode Frequency C1 pF C2 pF 740 EM78P312N 809N External RC Oscillator Mode OS CI Enwdtb = 0 Enable Enwdtb = 1 Disable Code Option RegisterCode Option Register Word Bit 12 ~ 9 Not used Power-on Considerations External Power-on Reset CircuitCustomer ID Register OSC = 0 RC type OSC = 1 Crystal type Residue-Voltage Protection VddEM78P312N EM78P809N Instruction Set Binary Instruction Hex Mnemonic Operation Status Binary Instruction Hex Mnemonic Operation Status Affected DEC Symbol Parameter Condition Min Typ Max Unit Absolute Maximum RatingsRecommended Operating Conditions Vss = DC Electrical Characteristics Ta= 25 C, VDD= 5.0V ± 5%, VSS= Ta= 25 C, VDD= 3.0V ± 5%, VSS= Varef Ta=- 40C ~ 85 C, VDD=5V ± 5%, VSS=0V AC Electrical CharacteristicSymbol Parameter Conditions Min Typ Max Unit Timing Diagram AC Test Input/Output Waveform OTP MCU Package TypePin Count Package Size EM78P311SxY