Receiving, Baud Rate Generator | IBM EM78P312N guide

EM78P312N

8-Bit Microcontroller

3.Start transmitting.

4.Serially transmitted data are transmitted in the following order from the TX pin.

5.Start bit: one “0” bit is output.

6.Transmit data: 7, 8 or 9 bits data are output from the LSB to the MSB.

7.Parity bit: one parity bit (odd or even selectable) is output.

8.Stop bit: one “1” bit (stop bit) is output.

Mark state: output “1” continues until the start bit of the next transmitted data.

After transmitting the stop bit, the UART generates a TBEF interrupt (if enabled).

5.7.3 Receiving

In receiving, the UART operates as follows:

1.Set RXE bit of the URS register to enable the UART receiving function.

The UART monitors the RX pin and synchronizes internally when it detects a start bit.

2.Receive data is shifted into the URRD register in the order from LSB to MSB.

3.The parity bit and the stop bit are received.

After one character received, the UART generates a RBFF interrupt (if enable). And URBF bit of URS register will be set to 1.

4.The UART makes the following checks:

(a)Parity check: The number of 1 of the received data must match the even or odd parity setting of the EVEN bit in the URS register.

(b)Frame check: The start bit must be 0 and the stop bit must be 1.

(c)Overrun check: The URBF bit of the URS register must be cleared (that means the URRD register should be read out) before next received data is loaded into the URRD register.

If any checks failed, the UERRIF interrupt will be generated (if enabled), and an error flag is indicated in PRERR, OVERR or FMERR bit. The error flag should be cleared by software else the UERRIF interrupt will occur when the next byte is received.

5.Read received data from URRD register. And URBF bit will be clear by hardware.

5.7.4 Baud Rate Generator

The baud rate generator is comprised of a circuit that generates a clock pulse to determine the transfer speed for transmission/reception in the UART.

The BRATE2~BRATE0 bits of the URC1 register can determine the desired baud rate.

30 •	Product Specification (V1.0) 10.03.2006

(This specification is subject to change without further notice)

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IBM EM78P312N manual Receiving, Baud Rate Generator

Contents

EM78P312N DOC. Version Elan Microelectronics Corporation Contents 16.2 14.116.1 16.3 General Description Bit Microcontroller Symbol Pin No Type Function Pin Description Functional Block Diagram Function Description Operating Registers Operating Registers R1 Time Clock /Counter Bit Microcontroller R0 Indirect Addressing RegisterR2 Program Counter & Stack Bit 7 ~ Bit 6 RBS1 ~ RBS0 R-Register page select User Memory SpaceR3 Status Register RBS1 RBS0 Bit 0 C Carry flag R4 RAM Select Register Bit 1 SIS Sleep and Idle mode selectSIS = 0 Idle mode SIS = 1 Sleep mode R5 System Control Register Bit 7 ~ Bit 0 P67 ~ P60 8-bit Port 6 I/O data register RB Timer/Counter 4 Control RegisterBit Microcontroller R6 Port 6 I/O Data Register R7 Port 7 I/O Data Register TC4CK2 TC4CK1 TC4CK0 RC Timer 4 Data BufferClock Source Resolution Max. Time Fosc=8M Bit Microcontroller RE Interrupt Status Flag Register RFInterrupt Status Flag Register Bank 1 R7 TC3DB Timer 3 Data Buffer B Bank 1 R5 TC3CR Timer/Counter 3 Control RegisterTC3M = 1 Capture mode Bank 1 R6 TC3DA Timer 3 Data Buffer a Bit 7 TC3CAP Software capture control TC2S = 0 Stop and counter clear Bank 1 R9 TC2DH Timer 2 Data Buffer High ByteBank 1 RA TC2DL Timer 2 Data Buffer Low Byte Bank 1 RB Adcr AD Control Register Bank 1 RC Adic AD Input Pin Control Bit 7 ~ Bit 0 ADE7 ~ ADE0 AD input pin enable controlBit 5~ Bit 4 ADCK1 ~ ADCK0 AD Conversion Time Select Bank 1 RD Addh AD High 8-bit Data Buffer Bank 2 R5 URC1 Uart Control Register TEN = 0 Disable TEN = 1 EnableBit Microcontroller Bank 1 RE Tbktc TBT/Keytone Control Bit BRATE2 BRATE1 BRATE0 Bank 2 R7 URS Uart Status RegisterBit 7 URRD8 Receiving data Bit TC2CK1 TC2CK0 Even = 0 Odd parity Even = 1 Even parity Bit 5 PRE Enable parity additionBit 6 Even Select parity check Bank 2 R9 Urtd Uart Transmit Data Buffer EDS = 0 Rising edge EDS = 1 Falling edge Bit 5 ~ Bit 3 BRS0 ~ BRS2 SPI Clock Source SelectBit 2 EDS Data shift out edge select Bit 0 WBE Write buffer empty flag. Read only Bank 3 RB PLC1 Pull Low Control Register PHE6x = 1 Disable P6x pull highTransfer Mode SPID7 SPID6 SPID5 SPID4 SPID3 SPID2 SPID1 SPID0 Special Purpose Registers INT1ES = 0 Rising edge INT1ES = 1 Falling edge IOC6 ~ IOC9 − I/O Port Control RegisterIntcr − INT Control Register Address 0Bh TC2ES = 0 Rising edge TC2ES = 1 Falling edge Adoscr − AD Offset Control Register Address 0Ch External InterruptCali Sign IMR2 − Interrupt Mask Register 2 Address 0Fh Uerrie Urie Utie Tbie EXIE1 TCIE0 Mode Switching Control CPU Operation ModeRegisters for CPU Operation Mode Operation Mode AD Converter Sleep Mode Idle ModeWake-up Signal R5 SIS = 1+SLEP R5 SIS= 0 + Slep Instruction Wake-up Methods Sampling Time Operation Mode Max. Frequency Max. Conversion Rate per BitADC Data Register Conversion Time Time Base Timer and Keytone Generator Address Name Bit MUX Registers for Uart Circuit Uart Universal Asynchronous Receiver/TransmitterName Bit Uart Mode Transmitting Receiving Baud Rate Generator Registers for the SPI Circuit SPI Serial Peripheral InterfaceRbank Address Name Bit Bit Transmit Mode Shift Direction and Sample PhaseTransfer Mode Serial Clock Bit Transmit/Receive Mode Bit Microcontroller Bit Receive ModeSCK pin Spis Multiple Device Connect /SS Timer/Counter Registers for Timer/Counter 2 Circuit Counter Mode Timer ModeWindow Mode Registers for Timer/Counter 3 Circuit 21 Window Mode Timing Chart Capture Mode 22 Configuration of Timer/Counter3 Registers for Timer 4 Circuit TCIF4 PDO Mode TCR4 Up-counter PWM Mode12 TCC/WDT & Prescaler TC4 Interrupt Reset Reset and Wake-up13 I/O Ports Wake-up from Sleep Mode Wake-up from Idle Mode Address Name Reset Type Bit Summary of the Initialized Values for Registers Bit Microcontroller Register Bank SCR Addres URTD8 Bit Microcontroller General Purpose Registers Reset TypeStatus of RST, T, and P of the Status Register Events that may affect the T and P Status 28 Controller Reset Block Diagram Interrupt Crystal Oscillator/Ceramic Resonators Crystal OscillatorOscillator Modes Summary of Maximum Operating Speeds Oscillator Type Frequency Mode Frequency C1 pF C2 pF 740 EM78P312N 809N External RC Oscillator Mode OS CI Code Option Register Word Enwdtb = 0 Enable Enwdtb = 1 DisableCode Option Register Bit 12 ~ 9 Not used Customer ID Register Power-on ConsiderationsExternal Power-on Reset Circuit OSC = 0 RC type OSC = 1 Crystal type EM78P312N Residue-Voltage ProtectionVdd EM78P809N Instruction Set Binary Instruction Hex Mnemonic Operation Status Binary Instruction Hex Mnemonic Operation Status Affected DEC Recommended Operating Conditions Symbol Parameter Condition Min Typ Max UnitAbsolute Maximum Ratings Vss = DC Electrical Characteristics Ta= 25 C, VDD= 5.0V ± 5%, VSS= Ta= 25 C, VDD= 3.0V ± 5%, VSS= Varef Symbol Parameter Conditions Min Typ Max Unit AC Electrical CharacteristicTa=- 40C ~ 85 C, VDD=5V ± 5%, VSS=0V Timing Diagram AC Test Input/Output Waveform Pin Count Package Size OTP MCUPackage Type EM78P311SxY