82555 10/100 Mbps LAN Physical Layer Interface | Intel instruction

82555 10/100 Mbps LAN Physical Layer Interface

Networking Silicon

Datasheet

Product Features

■ Optimal integration for lower cost solutions ■ Performance enhancements

—Integrated 10/100 Mbps single chip physical layer interface solution

—Complete 10/100 Mbps MII compliance with MDI support

—Full duplex operation in 10 Mbps and 100 Mbps modes

—IEEE 802.3u Auto-Negotiation support for 10BASE-T half and full duplex, 100BASE-TX half and full duplex, and 100BASE-T4 configurations

—Parallel detection algorithm for legacy support of non-Auto-Negotiation enabled link partner

—Integrated 10BASE-T transceiver with built in transmit and receive filters

—Glueless interface to T4-PHY for combination TX/T4 designs with single magnetics

—Glueless support for 4 LEDs: activity, link, speed, and duplex

—LED function mapping support via MDI

—Low external component count

—Single 25 MHz clock support for 10 Mbps and 100 Mbps (crystal or oscillator)

—Single magnetics for 10 Mbps and 100 Mbps operation

—QFP 100-pin package

—Flow control support for IEEE 802.3x Auto-Negotiation and Bay Technologies PHY Base* scheme

—Adaptive Channel Equalizer for greater functionality over varying cable lengths

—High tolerance to extreme noise conditions

—Very low emissions

—Jabber control circuitry to prevent data loss in 10 Mbps operation

—Auto-polarity correction for 10BASE-T

—Software compatible with 82557 drivers

■Repeater functionality

—Repeater mode operation

—Support for forced speed of 10 Mbps

and 100 Mbps

—Automatic carrier disconnect for IEEE 802.3u compliance

—Auto-Negotiation enable/disable capability

—Receive port enable function

—Support for 32 configurable addresses

—Narrow analog side (14 mm) for tight packing in repeater and switch designs

Notice:

Notice:

Document Number: 666252-004

Revision 2.0

March 1998

Image 1

Intel manual 82555 10/100 Mbps LAN Physical Layer Interface, Product Features

Contents

82555 10/100 Mbps LAN Physical Layer Interface Product Features Revision Description Networking Silicon Contents Repeater Mode Functional Overview IntroductionCompliance to Industry Standards Networking Silicon Architectural Overview 100 Mbps Mode MII TX Interface 10 Mbps Mode Media Independent Interface MII Repeater mode only Transmit Error From RICYes Pin Numbers and Labels Pin Definitions Twisted Pair Ethernet TPE Pins Clock PinsMedia Independent Interface MII Pins Pin Types Media Access Control/Repeater Interface Control Pins External Bias Pins LED Pins Miscellaneous Control Pins VCC Power and Ground PinsVSS Symbol 5B Symbol Code 4B Nibble Code 100BASE-TX Adapter Mode Operation100BASE-TX Transmit Clock Generation 100BASE-TX Transmit Blocks Invalid 2 100BASE-TX Scrambler and MLT-3 Encoder 3 100BASE-TX Transmit Framing NRZ to MLT-3 Encoding Diagram Transmit Driver 100BASE-TX Receive BlocksVendor Model/Type 100BASE-TX Collision Detection Combination Tx/T4 Auto-Negotiation Solution 100BASE-TX Link Integrity and Auto-Negotiation SolutionLink Integrity Auto-Negotiation Auto 10/100 Mbps Speed Selection Adapter Mode Addresses Networking Silicon Datasheet 10BASE-T Transmit Clock Generation 10BASE-T Functionality in Adapter Mode10BASE-T Transmit Blocks 10BASE-T Receive Blocks 10BASE-T Collision Detection 3 10BASE-T Error Detection and Reporting10BASE-T Link Integrity 10BASE-T Jabber Control Function 10BASE-T Full Duplex Networking Silicon Datasheet Special Repeater Features Repeater ModeConnectivity Clock Signal Example MDI Frame Structure Management Data Interface MDI Registers Bits Name Description DefaultMDI Registers 0 Transition 10BASE-T Register 1 Status Register Bit Definitions Register 2 82555 Identifier Register Bit Definitions MDI Registers 16 MDI Registers 8 100BASE-TX Register 17 82555 Special Control Bit Definitions 150 Actled Liled Register 22 Receive Symbol Error Counter Bit Definitions Auto-Negotiation Functionality Bit Setting TechnologyDescription Priority Technology Priority Parallel Detect and Auto-Negotiation Auto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Reset Reset and Miscellaneous Test ModesLoopback Scrambler Bypass Number Code Test Instruction Select Input to Tout Test Instruction Coding DC Characteristics Electrical Specifications and Timing ParametersAbsolute Maximum Ratings General Operating Conditions Total supply current 230 Leakage on analog pins 11.3.3 100BASE-TX Voltage/Current DC Characteristics MII Clock Specifications AC CharacteristicsSymbol Parameter Conditions Min Typ Max Units MII Clocks AC Timing MII Timing Parameters RXC tri-stated a Repeater Mode Timing Parameters Squelch Test Timing Parameters Transmit Packet Timing Parameters Receive Packet Timing Parameters Jabber Timing Parameters Auto-Negotiation Fast Link Pulse FLP Timing Parameters 11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters 11.4.11 X1 Clock Specifications Reset Timing Parameters X1 Clock Specifications 11.4.12 100BASE-TX Transmitter AC Specification 12.0 82555 Package Information Symbol Description Min Norm Max 10.0