MDI Registers 0, Transition | Intel 82555 specification

82555 — Networking Silicon

The 82555 address can be configured to four 0 through 3 in DTE (adapter) mode and 0 through 31 in repeater mode. A special functions for switches allows 32 addresses to exist in repeater mode. The management frame structure is as follows:

Transition	ST	OP	PHYAD	REGAD	TA	DATA


READ	<01>	<10>	<AAAAA>	<RRRRR>	<X0>	16 bits

WRITE	<01>	<01>	<AAAAA>	<RRRRR>	<10>	16 bits

7.2MDI Registers

MDI registers are described in the following subsections and the acronyms mentioned in the registers are defined as follows:

SC - Self Cleared.

RO -Read Only.

P- External pin affects 82555 register content.

LL- Latch Low. LH - Latch High.

7.2.1MDI Registers 0 - 7

7.2.1.1Register 0: Control Register Bit Definitions

Bit(s)	Name		Description	Default	R/W


15	Reset	This bit sets the status and control register of the 82555		0	RW
		to their default states and is self-clearing. The PHY			SC
		returns a value of 1b until the reset process has			SC
		returns a value of 1b until the reset process has
		completed and accepts a read or write transaction.
		1	= PHY Reset
		0	= Normal operation

14	Loopback	This bit enables loopback of transmit data nibbles from		0	RW
		the TXD[3:0] signals to the receive data path. The			P
		82555’s receive circuitry is isolated from the network.			P
		82555’s receive circuitry is isolated from the network.
		Note that this may cause the descrambler to lose
		synchronization and produce 560 nanoseconds of “dead
		time.”
		Note also that the loopback configuration bit takes priority
		over the Loopback MDI bit.
		1	= Loopback enabled
		0	= Loopback disabled (normal operation)

13	Speed Selection	This bit controls speed when Auto-Negotiation is disabled		1	RW
		and is valid on read when Auto-Negotiation is disabled.			P
					P
		1	= 100 Mbps
		0	= 10 Mbps

12	Auto-Negotiation	This bit enables Auto-Negotiation. Bits 13 and 8, Speed		1	RW
	Enable	Selection and Duplex Mode, respectively, are ignored
		when Auto-Negotiation is enabled.
		1	= Auto-Negotiation enabled
		0	= Auto-Negotiation disabled

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Datasheet

Image 32

Intel 82555 manual MDI Registers 0, Transition, Bits Name Description Default

Contents

Product Features 82555 10/100 Mbps LAN Physical Layer Interface Networking Silicon Revision Description Contents Repeater Mode Compliance to Industry Standards IntroductionFunctional Overview Networking Silicon 100 Mbps Mode Architectural Overview 10 Mbps Mode MII TX Interface Media Independent Interface MII Yes Transmit Error From RICRepeater mode only Pin Definitions Pin Numbers and Labels Clock Pins Twisted Pair Ethernet TPE PinsMedia Independent Interface MII Pins Pin Types Media Access Control/Repeater Interface Control Pins LED Pins External Bias Pins Miscellaneous Control Pins VSS Power and Ground PinsVCC 100BASE-TX Adapter Mode Operation Symbol 5B Symbol Code 4B Nibble Code100BASE-TX Transmit Clock Generation 100BASE-TX Transmit Blocks 2 100BASE-TX Scrambler and MLT-3 Encoder Invalid NRZ to MLT-3 Encoding Diagram 3 100BASE-TX Transmit Framing Vendor Model/Type 100BASE-TX Receive BlocksTransmit Driver 100BASE-TX Collision Detection 100BASE-TX Link Integrity and Auto-Negotiation Solution Combination Tx/T4 Auto-Negotiation SolutionLink Integrity Auto-Negotiation Adapter Mode Addresses Auto 10/100 Mbps Speed Selection Networking Silicon Datasheet 10BASE-T Functionality in Adapter Mode 10BASE-T Transmit Clock Generation10BASE-T Transmit Blocks 10BASE-T Receive Blocks 3 10BASE-T Error Detection and Reporting 10BASE-T Collision Detection10BASE-T Link Integrity 10BASE-T Jabber Control Function 10BASE-T Full Duplex Networking Silicon Datasheet Connectivity Repeater ModeSpecial Repeater Features Clock Signal Example Management Data Interface MDI Frame Structure Bits Name Description Default MDI RegistersMDI Registers 0 Transition Register 1 Status Register Bit Definitions 10BASE-T Register 2 82555 Identifier Register Bit Definitions MDI Registers 8 MDI Registers 16 Register 17 82555 Special Control Bit Definitions 100BASE-TX 150 Register 22 Receive Symbol Error Counter Bit Definitions Actled Liled Bit Setting Technology Auto-Negotiation FunctionalityDescription Priority Technology Parallel Detect and Auto-Negotiation Priority Auto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Reset and Miscellaneous Test Modes ResetLoopback Scrambler Bypass Test Instruction Coding Number Code Test Instruction Select Input to Tout Electrical Specifications and Timing Parameters DC CharacteristicsAbsolute Maximum Ratings General Operating Conditions 11.3.3 100BASE-TX Voltage/Current DC Characteristics Total supply current 230 Leakage on analog pins Symbol Parameter Conditions Min Typ Max Units AC CharacteristicsMII Clock Specifications MII Timing Parameters MII Clocks AC Timing Repeater Mode Timing Parameters RXC tri-stated a Transmit Packet Timing Parameters Squelch Test Timing Parameters Jabber Timing Parameters Receive Packet Timing Parameters 11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters Auto-Negotiation Fast Link Pulse FLP Timing Parameters Reset Timing Parameters 11.4.11 X1 Clock Specifications 11.4.12 100BASE-TX Transmitter AC Specification X1 Clock Specifications Symbol Description Min Norm Max 12.0 82555 Package Information 10.0