Intel 82555 11.4.10 Reset Timing Parameters , 11.4.11 X1 Clock Specifications

Datasheet 51
Networking Silicon — 82555
11.4.10 Reset Timing Parameters
11.4.11 X1 Clock Specifications
T33 TFLP_BUR_NUM Number of pulses in one burst 17 33
T34 TFLP_BUR_WID FLP Burst width 2 ms
T35 TFLP_BUR_PER FLP burst period 8 24 ms
Symbol Parameter Conditions Min Typ Max Units
Figure 24. Fast Link Pulse Timing Parameters
Fast Link Pulse
T31
T30
T30
Clock Pulse Data Pulse Clock Pulse
FLP Bursts
T34
T35
Symbol Parameter Conditions Min Typ Max Units
T36 TRST_WID Reset pulse width 5 00 ns
T37 TPUP_RST Power-up to falling edge of reset 500 µs
Figure 25. Reset Timing Parameters
Power Up
(
VCC
)
RESET
T37
T36
Symbol Parameter Conditions Min Typ Max Units
T38 TX1_DC X1 duty cycle 40 60 %
T39 TX1_PR X1 period ±50 PPM 40 ns