Media Independent Interface MII | Intel 82555 guide

Networking Silicon — 82555

The 82555 provides a glueless interface to Intel components such as the 82557 Fast Ethernet Controller, as well as any MII compatible device. Figure 4 shows a schematic-level diagram of the 82557 Fast Ethernet controller implementation connected to the 82555 using the MII interface.

	Flash	EEPR O M
	(optional)	(optional)
		RXD[3:0]
		RXC
		RXERR
		RXDV
		CRS
		COL
	82557	TXD[3:0]	82555
	82557	TXC	82555
		TXC
		TXEN
		MDC
		MDIO
		RESET
	PCI Bus Signals

Figure 4. Intel 82557/82555 Solution

2.3Media Independent Interface (MII)

The 82555 supports the Media Independent Interface (MII) as its primary interface to the MAC. The MII Interface is summarized in Table 1.

Table 1. 82555 MII

	Signal	Description	Direction	Clock	MII Signal Supported
	Name	Description	Direction	Reference	by the 82555?
	Name			Reference	by the 82555?

	TXC	Transmit Clock	From 82555	--	Yes
	TXC	Transmit Clock	(adapter mode only)	--	Yes
			(adapter mode only)

	TXD[3:0]	Transmit Data	From MAC	TXC	Yes

	TXEN	Transmit Enable	From MAC	TXC	Yes

	COL	Collision Detect	From 82555	Asynchronous	Yes

	CRS	Carrier Sense	From 82555	Asynchronous	Yes

	RXC	Receive Clock	From 82555	--	Yes

	RXD[3:0]	Receive Data	From 82555	RXC	Yes

	RXDV	Receive Data Valid	From 82555	RXC	Yes

	RXERR	Receive Error	From 82555	RXC	Yes

	MDC	Management Data	From manager	--	Yes
	MDC	Clock	From manager	--	Yes
		Clock

	MDIO	Management Data	From manager	MDC	Yes
	MDIO	Input/Output	From manager	MDC	Yes
		Input/Output

Datasheet

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Image 9

Intel 82555 manual Media Independent Interface MII

Contents

82555 10/100 Mbps LAN Physical Layer Interface Product Features Revision Description Networking Silicon Contents Repeater Mode Introduction Functional OverviewCompliance to Industry Standards Networking Silicon Architectural Overview 100 Mbps Mode MII TX Interface 10 Mbps Mode Media Independent Interface MII Transmit Error From RIC Repeater mode onlyYes Pin Numbers and Labels Pin Definitions Twisted Pair Ethernet TPE Pins Clock PinsMedia Independent Interface MII Pins Pin Types Media Access Control/Repeater Interface Control Pins External Bias Pins LED Pins Miscellaneous Control Pins Power and Ground Pins VCCVSS Symbol 5B Symbol Code 4B Nibble Code 100BASE-TX Adapter Mode Operation100BASE-TX Transmit Clock Generation 100BASE-TX Transmit Blocks Invalid 2 100BASE-TX Scrambler and MLT-3 Encoder 3 100BASE-TX Transmit Framing NRZ to MLT-3 Encoding Diagram 100BASE-TX Receive Blocks Transmit DriverVendor Model/Type 100BASE-TX Collision Detection Combination Tx/T4 Auto-Negotiation Solution 100BASE-TX Link Integrity and Auto-Negotiation SolutionLink Integrity Auto-Negotiation Auto 10/100 Mbps Speed Selection Adapter Mode Addresses Networking Silicon Datasheet 10BASE-T Transmit Clock Generation 10BASE-T Functionality in Adapter Mode10BASE-T Transmit Blocks 10BASE-T Receive Blocks 10BASE-T Collision Detection 3 10BASE-T Error Detection and Reporting10BASE-T Link Integrity 10BASE-T Jabber Control Function 10BASE-T Full Duplex Networking Silicon Datasheet Repeater Mode Special Repeater FeaturesConnectivity Clock Signal Example MDI Frame Structure Management Data Interface MDI Registers Bits Name Description DefaultMDI Registers 0 Transition 10BASE-T Register 1 Status Register Bit Definitions Register 2 82555 Identifier Register Bit Definitions MDI Registers 16 MDI Registers 8 100BASE-TX Register 17 82555 Special Control Bit Definitions 150 Actled Liled Register 22 Receive Symbol Error Counter Bit Definitions Auto-Negotiation Functionality Bit Setting TechnologyDescription Priority Technology Priority Parallel Detect and Auto-Negotiation Auto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Reset Reset and Miscellaneous Test ModesLoopback Scrambler Bypass Number Code Test Instruction Select Input to Tout Test Instruction Coding DC Characteristics Electrical Specifications and Timing ParametersAbsolute Maximum Ratings General Operating Conditions Total supply current 230 Leakage on analog pins 11.3.3 100BASE-TX Voltage/Current DC Characteristics AC Characteristics MII Clock SpecificationsSymbol Parameter Conditions Min Typ Max Units MII Clocks AC Timing MII Timing Parameters RXC tri-stated a Repeater Mode Timing Parameters Squelch Test Timing Parameters Transmit Packet Timing Parameters Receive Packet Timing Parameters Jabber Timing Parameters Auto-Negotiation Fast Link Pulse FLP Timing Parameters 11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters 11.4.11 X1 Clock Specifications Reset Timing Parameters X1 Clock Specifications 11.4.12 100BASE-TX Transmitter AC Specification 12.0 82555 Package Information Symbol Description Min Norm Max 10.0