82555 — Networking Silicon

Low power consumption

Typical total solution power including all resistors and magnetics:

-275 mA 100BASE-TX

-230 mA 10BASE-T

-250 mA Auto-Negotiation

300 mA maximum total solution power in DTE (adapter) mode

Power-down of 10BASE-T/100BASE- TX sections when not in use

Revision History

Added modes for design, testing, and manufacturability

Test Access Port (TAP)

-NAND Tree

-Board Level Functional Test (BIST)

Programmable bypass for 4B/5B encoding/decoding and scrambler/ descrambler

Diagnostic loopback mode

Revision

Revision

Description

Date

 

 

 

 

 

Jan. 1997

1.0

First external release of the preliminary datasheet

 

 

 

Apr. 1997

1.1

First release edition

 

 

 

Mar. 1998

2.0

General editing

 

 

 

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Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 82555 10/100 Mbps LAN Physical Layer Interface may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

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Copyright © Intel Corporation, 1997

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Datasheet

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Intel 82555 manual Networking Silicon, Revision Description