Register 17 82555 Special Control Bit Definitions | Intel instruction

82555 — Networking Silicon

7.2.3.1Register 16: 82555 Status and Control Register Bit Definitions

Bit(s)	Name		Description	Default	R/W


15	Flow Control	This bit enables PHY Base (Bay Technologies) flow		0	RW
		control.
		1	= Enable PHY Base flow control
		0	= Disable PHY Base flow control

14	Reserved	These bits are reserved and should be set to 0b		0	RW

13	Carrier Sense	This bit enables the disconnect function.		0 (DTE	RW
	Disconnect	1	= Disconnect function enabled (default in DTE)	1 (Rptr)
	Control	1	= Disconnect function enabled (default in DTE)	1 (Rptr)
	Control	0	= Disconnect function disabled (default in repeater)
		0	= Disconnect function disabled (default in repeater)

12	Transmit Flow	This bit enables Transmit Flow Control		0	RW
	Control Disable	1	= Transmit Flow Control enabled
		1	= Transmit Flow Control enabled
		0	= Transmit Flow Control disabled

11	Receive De-	This bit indicates status of the 100BASE-TX Receive		--	RO
	Serializer In-Sync	De-Serializer In-Sync.
	Indication

10	100BASE-TX	This bit indicates the power state of 100BASE-TX		--	RO
	Power-Down	82555.
		1	= Power-down
		0	= Normal operation

9	10BASE-T	This bit indicates the power state of 10BASE-TX		--	RO
	Power-Down	82555.
		1	= Power-Down
		0	= Normal operation

8	Polarity	This bit indicates 10BASE-T polarity.		--	RO
		1	= Reverse polarity
		0	= Normal polarity

7:3	Reserved	These bits are reserved and should be set to a		00000	RO
		constant 0.

2	T4	This bit indicates the Auto-Negotiation result.		--	RO
		1	= 100BASE-T4
		0	= No 100BASE-T4

1	Speed	This bit indicates the Auto-Negotiation result.		--	RO
		1	= 100 Mbps
		0	= 10 Mbps

0	Duplex Mode	This bit indicates the Auto-Negotiation result.		--	RO
		1	= Full Duplex
		0	= Half Duplex

7.2.3.2Register 17: 82555 Special Control Bit Definitions

Bit(s)	Name		Description	Default	R/W


15	Scrambler By-	1	= By-pass Scrambler	0	RW
	pass	0	= Normal operations
		0	= Normal operations

14	By-pass 4B/5B	1 = 4 bit to 5 bit by-pass		0	RW
		0	= Normal operation

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Datasheet

Image 36

Intel manual Register 17 82555 Special Control Bit Definitions, 100BASE-TX

Contents

Product Features 82555 10/100 Mbps LAN Physical Layer Interface Networking Silicon Revision Description Contents Repeater Mode Introduction Functional OverviewCompliance to Industry Standards Networking Silicon 100 Mbps Mode Architectural Overview 10 Mbps Mode MII TX Interface Media Independent Interface MII Transmit Error From RIC Repeater mode onlyYes Pin Definitions Pin Numbers and Labels Clock Pins Twisted Pair Ethernet TPE PinsMedia Independent Interface MII Pins Pin Types Media Access Control/Repeater Interface Control Pins LED Pins External Bias Pins Miscellaneous Control Pins Power and Ground Pins VCCVSS 100BASE-TX Adapter Mode Operation Symbol 5B Symbol Code 4B Nibble Code100BASE-TX Transmit Clock Generation 100BASE-TX Transmit Blocks 2 100BASE-TX Scrambler and MLT-3 Encoder Invalid NRZ to MLT-3 Encoding Diagram 3 100BASE-TX Transmit Framing 100BASE-TX Receive Blocks Transmit DriverVendor Model/Type 100BASE-TX Collision Detection 100BASE-TX Link Integrity and Auto-Negotiation Solution Combination Tx/T4 Auto-Negotiation SolutionLink Integrity Auto-Negotiation Adapter Mode Addresses Auto 10/100 Mbps Speed Selection Networking Silicon Datasheet 10BASE-T Functionality in Adapter Mode 10BASE-T Transmit Clock Generation10BASE-T Transmit Blocks 10BASE-T Receive Blocks 3 10BASE-T Error Detection and Reporting 10BASE-T Collision Detection10BASE-T Link Integrity 10BASE-T Jabber Control Function 10BASE-T Full Duplex Networking Silicon Datasheet Repeater Mode Special Repeater FeaturesConnectivity Clock Signal Example Management Data Interface MDI Frame Structure Bits Name Description Default MDI RegistersMDI Registers 0 Transition Register 1 Status Register Bit Definitions 10BASE-T Register 2 82555 Identifier Register Bit Definitions MDI Registers 8 MDI Registers 16 Register 17 82555 Special Control Bit Definitions 100BASE-TX 150 Register 22 Receive Symbol Error Counter Bit Definitions Actled Liled Bit Setting Technology Auto-Negotiation FunctionalityDescription Priority Technology Parallel Detect and Auto-Negotiation Priority Auto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Reset and Miscellaneous Test Modes ResetLoopback Scrambler Bypass Test Instruction Coding Number Code Test Instruction Select Input to Tout Electrical Specifications and Timing Parameters DC CharacteristicsAbsolute Maximum Ratings General Operating Conditions 11.3.3 100BASE-TX Voltage/Current DC Characteristics Total supply current 230 Leakage on analog pins AC Characteristics MII Clock SpecificationsSymbol Parameter Conditions Min Typ Max Units MII Timing Parameters MII Clocks AC Timing Repeater Mode Timing Parameters RXC tri-stated a Transmit Packet Timing Parameters Squelch Test Timing Parameters Jabber Timing Parameters Receive Packet Timing Parameters 11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters Auto-Negotiation Fast Link Pulse FLP Timing Parameters Reset Timing Parameters 11.4.11 X1 Clock Specifications 11.4.12 100BASE-TX Transmitter AC Specification X1 Clock Specifications Symbol Description Min Norm Max 12.0 82555 Package Information 10.0