Pin Types, Clock Pins, Twisted Pair Ethernet TPE Pins | Intel 82555

82555 — Networking Silicon

Pin allocation is based on a 100-lead quad flat package. All pin locations are based on printed circuit board layout and other design constraints.

3.1Pin Types

Pin Type	Description


I	This type of pin is an input pin to the 82555.

O	This type of pin is an output pin from the 82555.

I/O	This type of pin is both an input and output pin for the 82555.

BThis pin is used as a bias pin. The bias pin is either pulled up or down with a resistor. The bias pin may also be used as an external voltage reference.

3.2Clock Pins

Symbol	Pin	Type	Name and Function


X1	56	I	Crystal Input One. X1 and X2 can be driven by an external 25 MHz crystal.
			Otherwise, X1 may be driven by an external MOS level 25 MHz oscillator
			when X2 is left floating. (The crystal should have a tolerance of 50 PPM or
			better.)

X2	55	O	Crystal Output Two. X1 and X2 can be driven by an external 25 MHz
			crystal. Otherwise, X1 may be driven by an external MOS level 25 MHz
			oscillator when this pin is left floating.

3.3Twisted Pair Ethernet (TPE) Pins

Symbol	Pin	Type	Name and Function


TDP	47	O	Transmit Differential Pair. These pins send the serial bitstream for
TDN	48		transmission on an unshielded twisted pair (UTP) cable. The current-driven
TDN	48		differential driver can be two-level (10BASE-T or Manchester) or three-level

			(100BASE-TX or MLT-3) signals depending on the operating mode. These
			signals interface directly with an isolation transformer.

RDP	33	I	Receive Differential Pair. These pins receive the serial bitstream from the
RDN	34		isolation transformer. The bitstream can be two-level (10BASE-T or
RDN	34		manchester) or three-level (100BASE-TX or MLT-3) signals depending on the

			operating mode.

3.4Media Independent Interface (MII) Pins

Symbol	Pin	Type	Name and Function


RXD3	97	O	Receive Data. In 100 Mbps and 10 Mbps mode, data is transferred across
RXD2	96		these four lines one nibble at a time.
RXD2	96
RXD1	95
RXD0	92

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Datasheet

Image 12

Intel 82555 manual Pin Types, Clock Pins, Twisted Pair Ethernet TPE Pins, Media Independent Interface MII Pins

Contents

Product Features 82555 10/100 Mbps LAN Physical Layer Interface Networking Silicon Revision Description Contents Repeater Mode Introduction Functional OverviewCompliance to Industry Standards Networking Silicon 100 Mbps Mode Architectural Overview 10 Mbps Mode MII TX Interface Media Independent Interface MII Transmit Error From RIC Repeater mode onlyYes Pin Definitions Pin Numbers and Labels Clock Pins Twisted Pair Ethernet TPE PinsMedia Independent Interface MII Pins Pin Types Media Access Control/Repeater Interface Control Pins LED Pins External Bias Pins Miscellaneous Control Pins Power and Ground Pins VCCVSS 100BASE-TX Adapter Mode Operation Symbol 5B Symbol Code 4B Nibble Code100BASE-TX Transmit Clock Generation 100BASE-TX Transmit Blocks 2 100BASE-TX Scrambler and MLT-3 Encoder Invalid NRZ to MLT-3 Encoding Diagram 3 100BASE-TX Transmit Framing 100BASE-TX Receive Blocks Transmit DriverVendor Model/Type 100BASE-TX Collision Detection 100BASE-TX Link Integrity and Auto-Negotiation Solution Combination Tx/T4 Auto-Negotiation SolutionLink Integrity Auto-Negotiation Adapter Mode Addresses Auto 10/100 Mbps Speed Selection Networking Silicon Datasheet 10BASE-T Functionality in Adapter Mode 10BASE-T Transmit Clock Generation10BASE-T Transmit Blocks 10BASE-T Receive Blocks 3 10BASE-T Error Detection and Reporting 10BASE-T Collision Detection10BASE-T Link Integrity 10BASE-T Jabber Control Function 10BASE-T Full Duplex Networking Silicon Datasheet Repeater Mode Special Repeater FeaturesConnectivity Clock Signal Example Management Data Interface MDI Frame Structure Bits Name Description Default MDI RegistersMDI Registers 0 Transition Register 1 Status Register Bit Definitions 10BASE-T Register 2 82555 Identifier Register Bit Definitions MDI Registers 8 MDI Registers 16 Register 17 82555 Special Control Bit Definitions 100BASE-TX 150 Register 22 Receive Symbol Error Counter Bit Definitions Actled Liled Bit Setting Technology Auto-Negotiation FunctionalityDescription Priority Technology Parallel Detect and Auto-Negotiation Priority Auto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Reset and Miscellaneous Test Modes ResetLoopback Scrambler Bypass Test Instruction Coding Number Code Test Instruction Select Input to Tout Electrical Specifications and Timing Parameters DC CharacteristicsAbsolute Maximum Ratings General Operating Conditions 11.3.3 100BASE-TX Voltage/Current DC Characteristics Total supply current 230 Leakage on analog pins AC Characteristics MII Clock SpecificationsSymbol Parameter Conditions Min Typ Max Units MII Timing Parameters MII Clocks AC Timing Repeater Mode Timing Parameters RXC tri-stated a Transmit Packet Timing Parameters Squelch Test Timing Parameters Jabber Timing Parameters Receive Packet Timing Parameters 11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters Auto-Negotiation Fast Link Pulse FLP Timing Parameters Reset Timing Parameters 11.4.11 X1 Clock Specifications 11.4.12 100BASE-TX Transmitter AC Specification X1 Clock Specifications Symbol Description Min Norm Max 12.0 82555 Package Information 10.0