Introduction, Functional Overview | Intel 82555 manual

Networking Silicon — 82555

1.0Introduction

The 82555 is a highly integrated, physical layer interface solution designed for 10 and 100 Mbps Ethernet systems based on the IEEE 10BASE-T and 100BASE-TX specifications. 100BASE-TX is an IEEE 802.3 physical layer specification for use over two pairs of Category 5 unshielded twisted pair or Type 1 shielded twisted pair cable. 100BASE-TX defines a signaling scheme not only for 100 Mbps, but also provides CSMA/CD compatibility with the 10 Mbps IEEE 802.3 10BASE-T signaling standard.

1.1Functional Overview

The 82555 is designed to work in two modes: Data Terminal Equipment (DTE) for adapters and repeater for hubs and switches. When configured to DTE (adapter) mode, the 82555 incorporates all active circuitry required to interface 10/100 Mbps Ethernet controllers and CSMA/CD MAC components to 10 Mbps and 100 Mbps networks. In this and other documents the 82555 may be referred to as the DTE, Physical Medium Device (PMD), or Physical Layer Medium (PLM). It supports a direct glueless interface to Intel components such as the 82557 Fast Ethernet controller. The 82555 also supports the Media Independent Interface (MII) signals as specified in the IEEE 802.3u standard. The figure below shows how the 82555 fits into a 10/100 Mbps Ethernet adapter design.

Pair 1

Intel 82555

Controller/MAC

Pair 2

Magnetics

System Bus Interface

Figure 1. 82555 10/100 Mbps Ethernet Solution

When configured to repeater mode, the 82555 incorporates several features that allow it to function as a Class I or MII level repeater. Section 6.0, “Repeater Mode” on page 25 describes the 82555 in a repeater type of application.

1.2Compliance to Industry Standards

When operating in 100 Mbps mode, the 82555 complies with IEEE 802.3u 100BASE-TX specification. The PMD section with the related changes established in 802.3u 100BASE-TX complies with ANSI X3.263:1995 TP-PMD, Revision 2.2.

When operating in the 10 Mbps mode, the 82555 complies with the IEEE 802.3 10BASE-T specification.

Datasheet

1

Image 5

Intel 82555 manual Introduction, Functional Overview, Compliance to Industry Standards

Contents

82555 10/100 Mbps LAN Physical Layer Interface Product Features Revision Description Networking Silicon Contents Repeater Mode Compliance to Industry Standards IntroductionFunctional Overview Networking Silicon Architectural Overview 100 Mbps Mode MII TX Interface 10 Mbps Mode Media Independent Interface MII Yes Transmit Error From RICRepeater mode only Pin Numbers and Labels Pin Definitions Twisted Pair Ethernet TPE Pins Clock PinsMedia Independent Interface MII Pins Pin Types Media Access Control/Repeater Interface Control Pins External Bias Pins LED Pins Miscellaneous Control Pins VSS Power and Ground PinsVCC Symbol 5B Symbol Code 4B Nibble Code 100BASE-TX Adapter Mode Operation100BASE-TX Transmit Clock Generation 100BASE-TX Transmit Blocks Invalid 2 100BASE-TX Scrambler and MLT-3 Encoder 3 100BASE-TX Transmit Framing NRZ to MLT-3 Encoding Diagram Vendor Model/Type 100BASE-TX Receive BlocksTransmit Driver 100BASE-TX Collision Detection Combination Tx/T4 Auto-Negotiation Solution 100BASE-TX Link Integrity and Auto-Negotiation SolutionLink Integrity Auto-Negotiation Auto 10/100 Mbps Speed Selection Adapter Mode Addresses Networking Silicon Datasheet 10BASE-T Transmit Clock Generation 10BASE-T Functionality in Adapter Mode10BASE-T Transmit Blocks 10BASE-T Receive Blocks 10BASE-T Collision Detection 3 10BASE-T Error Detection and Reporting10BASE-T Link Integrity 10BASE-T Jabber Control Function 10BASE-T Full Duplex Networking Silicon Datasheet Connectivity Repeater ModeSpecial Repeater Features Clock Signal Example MDI Frame Structure Management Data Interface MDI Registers Bits Name Description DefaultMDI Registers 0 Transition 10BASE-T Register 1 Status Register Bit Definitions Register 2 82555 Identifier Register Bit Definitions MDI Registers 16 MDI Registers 8 100BASE-TX Register 17 82555 Special Control Bit Definitions 150 Actled Liled Register 22 Receive Symbol Error Counter Bit Definitions Auto-Negotiation Functionality Bit Setting TechnologyDescription Priority Technology Priority Parallel Detect and Auto-Negotiation Auto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Reset Reset and Miscellaneous Test ModesLoopback Scrambler Bypass Number Code Test Instruction Select Input to Tout Test Instruction Coding DC Characteristics Electrical Specifications and Timing ParametersAbsolute Maximum Ratings General Operating Conditions Total supply current 230 Leakage on analog pins 11.3.3 100BASE-TX Voltage/Current DC Characteristics Symbol Parameter Conditions Min Typ Max Units AC CharacteristicsMII Clock Specifications MII Clocks AC Timing MII Timing Parameters RXC tri-stated a Repeater Mode Timing Parameters Squelch Test Timing Parameters Transmit Packet Timing Parameters Receive Packet Timing Parameters Jabber Timing Parameters Auto-Negotiation Fast Link Pulse FLP Timing Parameters 11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters 11.4.11 X1 Clock Specifications Reset Timing Parameters X1 Clock Specifications 11.4.12 100BASE-TX Transmitter AC Specification 12.0 82555 Package Information Symbol Description Min Norm Max 10.0