Register 2 82555 Identifier Register Bit Definitions | Intel

82555 — Networking Silicon

Bit(s)	Name		Description	Default	R/W


6	Management	1	= 82555 will accept management frames with	--	RO
	Frames Preamble	preamble suppressed
	Suppression	0	= 82555 will not accept management frames with
		0	= 82555 will not accept management frames with
		preamble suppressed

5	Auto-Negotiation	1	= Auto-Negotiation process completed	0	RO
	Complete	0	= Auto-Negotiation process has not completed
		0	= Auto-Negotiation process has not completed

4	Remote Fault	1	= Remote fault condition detected	0	RO
		0	= No remote fault condition detected		P

3	Auto-Negotiation	1	= 82555 is able to perform Auto-Negotiation	1	RO
	Ability	0	= 82555 is in repeater mode and Auto-Negotiation
		0	= 82555 is in repeater mode and Auto-Negotiation
		Disable pin is high

2	Link Status	1	= Valid link has been established	0	RO
		0	= Invalid link detected		LL
					SC

1	Jabber Detect	1	= Jabber condition detected	0	RO
		0	= No jabber condition detected		LH
					SC

0	Extended	1	= Extended register capabilities enabled	1	RO
	Capability	0	= No extended register capabilities
		0	= No extended register capabilities

7.2.1.3Register 2: 82555 Identifier Register Bit Definitions

Bit(s)	Name	Description	Default	R/W


15:0	82555 ID (high	Value: 02A8H	--	RO
	byte)

7.2.1.4Register 3: 82555 Identifier Register Bit Definitions

Bit(s)	Name	Description	Default	R/W


15:0	82555 ID (low	Value: 0150H	--	RO
	byte)

7.2.1.5Register 4: Auto-Negotiation Advertisement Register Bit Definitions

Bit(s)	Name	Description	Default	R/W


15	Next Page	Constant 0 = Transmitting primary capability data	--	RO
		page

14	Reserved	This bit is reserved and should be set to 0b.	0	RO

13	Remote Fault	1 = Indicate link partner’s remote fault	0	RW
		0 = No remote fault

12:5	Technology Ability	Technology Ability Field is an 8-bit field containing	--	RW
	Field	information indicating supported technologies specific
		to the selector field value.

4:0	Selector Field	The Selector Field is a 5-bit field identifying the type of	00001	RO
		message to be sent via Auto-Negotiation. This field is
		read only in the 82555 and contains a value of
		00001b, IEEE Standard 802.3.

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Datasheet

Image 34

Intel manual Register 2 82555 Identifier Register Bit Definitions

Contents

Product Features 82555 10/100 Mbps LAN Physical Layer Interface Networking Silicon Revision Description Contents Repeater Mode Functional Overview IntroductionCompliance to Industry Standards Networking Silicon 100 Mbps Mode Architectural Overview 10 Mbps Mode MII TX Interface Media Independent Interface MII Repeater mode only Transmit Error From RICYes Pin Definitions Pin Numbers and Labels Media Independent Interface MII Pins Clock PinsTwisted Pair Ethernet TPE Pins Pin Types Media Access Control/Repeater Interface Control Pins LED Pins External Bias Pins Miscellaneous Control Pins VCC Power and Ground PinsVSS 100BASE-TX Transmit Clock Generation 100BASE-TX Adapter Mode OperationSymbol 5B Symbol Code 4B Nibble Code 100BASE-TX Transmit Blocks 2 100BASE-TX Scrambler and MLT-3 Encoder Invalid NRZ to MLT-3 Encoding Diagram 3 100BASE-TX Transmit Framing Transmit Driver 100BASE-TX Receive BlocksVendor Model/Type 100BASE-TX Collision Detection Link Integrity 100BASE-TX Link Integrity and Auto-Negotiation SolutionCombination Tx/T4 Auto-Negotiation Solution Auto-Negotiation Adapter Mode Addresses Auto 10/100 Mbps Speed Selection Networking Silicon Datasheet 10BASE-T Transmit Blocks 10BASE-T Functionality in Adapter Mode10BASE-T Transmit Clock Generation 10BASE-T Receive Blocks 10BASE-T Link Integrity 3 10BASE-T Error Detection and Reporting10BASE-T Collision Detection 10BASE-T Jabber Control Function 10BASE-T Full Duplex Networking Silicon Datasheet Special Repeater Features Repeater ModeConnectivity Clock Signal Example Management Data Interface MDI Frame Structure MDI Registers 0 Bits Name Description DefaultMDI Registers Transition Register 1 Status Register Bit Definitions 10BASE-T Register 2 82555 Identifier Register Bit Definitions MDI Registers 8 MDI Registers 16 Register 17 82555 Special Control Bit Definitions 100BASE-TX 150 Register 22 Receive Symbol Error Counter Bit Definitions Actled Liled Description Bit Setting TechnologyAuto-Negotiation Functionality Priority Technology Parallel Detect and Auto-Negotiation Priority Auto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Loopback Reset and Miscellaneous Test ModesReset Scrambler Bypass Test Instruction Coding Number Code Test Instruction Select Input to Tout Absolute Maximum Ratings Electrical Specifications and Timing ParametersDC Characteristics General Operating Conditions 11.3.3 100BASE-TX Voltage/Current DC Characteristics Total supply current 230 Leakage on analog pins MII Clock Specifications AC CharacteristicsSymbol Parameter Conditions Min Typ Max Units MII Timing Parameters MII Clocks AC Timing Repeater Mode Timing Parameters RXC tri-stated a Transmit Packet Timing Parameters Squelch Test Timing Parameters Jabber Timing Parameters Receive Packet Timing Parameters 11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters Auto-Negotiation Fast Link Pulse FLP Timing Parameters Reset Timing Parameters 11.4.11 X1 Clock Specifications 11.4.12 100BASE-TX Transmitter AC Specification X1 Clock Specifications Symbol Description Min Norm Max 12.0 82555 Package Information 10.0