Main
82555 10/100 Mbps LAN Physical Layer Interface
Networking Silicon
Datasheet
Product Features
Page
Page
Contents
1.0 Introduction
1.1 Functional Overview
1.2 Compliance to Industry Standards
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2.0 Architectural Overview
2.1 100 Mbps Mode
2.2 10 Mbps Mode
Magnetics Module
Datasheet 5
g
Figure 4. Intel 82557/82555 Solution
2.3 Media Independent Interface (MII)
82555
82557
PCI Bus Si
nals
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8 Datasheet
3.1 Pin Types
3.2 Clock Pins
3.4 Media Independent Interface (MII) Pins
3.3 Twisted Pair Ethernet (TPE) Pins
3.5 Media Access Control/Repeater Interface Control Pins
Datasheet 9
10 Datasheet
3.6 LED Pins
3.7 External Bias Pins
Datasheet 11
3.8 Miscellaneous Control Pins
3.9 Power and Ground Pins
4.0 100BASE-TX Adapter Mode Operation
4.1 100BASE-TX Transmit Clock Generation
4.2 100BASE-TX Transmit Blocks
4.2.1 100BASE-TX 4B/5B Encoder
4.2.2 100BASE-TX Scrambler and MLT-3 Encoder
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4.2.4 Transmit Driver
4.3 100BASE-TX Receive Blocks
4.4 100BASE-TX Collision Detection
4.5 100BASE-TX Link Integrity and Auto-Negotiation Solution
4.5.1 Link Integrity
4.5.2 Auto-Negotiation
4.5.3 Combination Tx/T4 Auto-Negotiation Solution
4.6 Auto 10/100 Mbps Speed Selection
4.7 Adapter Mode Addresses
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5.0 10BASE-T Functionality in Adapter Mode
5.1 10BASE-T Transmit Clock Generation
5.2 10BASE-T Transmit Blocks
5.2.1 10BASE-T Manchester Encoder
5.2.2 10BASE-T Driver and Filter
5.4 10BASE-T Collision Detection
5.5 10BASE-T Link Integrity
5.6 10BASE-T Jabber Control Function
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6.0 Repeater Mode
6.1 Special Repeater Features
6.2 Connectivity
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7.0 Management Data Interface
7.1 MDI Frame Structure
7.2 MDI Registers
7.2.1 MDI Registers 0 - 7
7.2.1.1 Register 0: Control Register Bit Definitions
7.2.1.2 Register 1: Status Register Bit Definitions
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Datasheet 31
7.2.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Bit Definitions
Register numbers 16, 17, 20, 21, 22, 23, 24, 25, and 27 are described in the following subsections.
7.2.1.7 Register 6: Auto-Negotiation Expansion Register Bit Definitions
7.2.2 MDI Registers 8 - 15
Registers eight through fifteen are reserved for IEEE.
7.2.3 MDI Registers 16 - 31
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7.2.3.1 Register 16: 82555 Status and Control Register Bit Definitions
7.2.3.2 Register 17: 82555 Special Control Bit Definitions
Datasheet 33
7.2.3.3 Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions
7.2.3.4 Register 21: 100BASE-TX Receive Error Frame Counter Bit Definitions
34 Datasheet
7.2.3.5 Register 22: Receive Symbol Error Counter Bit Definitions
7.2.3.6 Register 23: 100BASE-TX Receive Premature End of Frame Error Counter Bit Definitions
7.2.3.9 Register 27: 82555 Special Control Bit Definitions
7.2.3.7 Register 24: 10BASE-T Receive End of Frame Error Counter Bit Definitions
7.2.3.8 Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions
8.0 Auto-Negotiation Functionality
8.1 Description
8.2 Parallel Detect and Auto-Negotiation
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9.0 LED Descriptions
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10.0 Reset and Miscellaneous Test Modes
10.1 Reset
10.2 Loopback
10.3 Scrambler Bypass
10.4 Test Port
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Datasheet 43
11.0 Electrical Specifications and Timing Parameters
11.1 Absolute Maximum Ratings
11.3.2 10BASE-T Voltage/Current DC Characteristics
11.2 General Operating Conditions 11.3 DC Characteristics
11.3.1 MII DC Characteristics
Icct10
105mA 110mA 115mA
Figure 11. RBIAS10 Resistance versus I
44 Datasheet
768
Icct100
38mA 40mA 42mA
604
634
Figure 12. RBIAS100 Resistance versus I
11.4.2 MII Timing Parameters
T1,T2,T3
Figure 15. MII Transmit Timing Parameters
Figure 14. MII Clocks AC Timing
46 Datasheet
11.4.3 Repeater Mode Timing Parameters
Datasheet 47
Figure 16. MII Receive Timing Parameters
Figure 18. PORT Enable Timing
Figure 17. MII Timing Parameters: MDC/MDIO
11.4.4 Transmit Packet Timing Parameters
Figure 19. Transmit Frame Timing Parameters
11.4.5 Squelch Test Timing Parameters
Datasheet 49
Figure 20. Squelch Test Timing Parameters
11.4.6 Jabber Timing Parameters
11.4.7 Receive Packet Timing Parameters
50 Datasheet
Figure 22. Receive Packet Timing Parameters
11.4.8 10BASE-T Normal Link Pulse (NLP) Timing Parameters
11.4.9 Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters
Figure 23. Normal Link Pulse Timing Parameters
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Networking Silicon 82555
11.4.10 Reset Timing Parameters
11.4.11 X1 Clock Specifications
11.4.12 100BASE-TX Transmitter AC Specification
12.0 82555 Package Information