Actled Liled | Intel 82555 specs

82555 — Networking Silicon

7.2.3.5Register 22: Receive Symbol Error Counter Bit Definitions

Bit(s)	Name	Description	Default	R/W


15:0	Symbol Error	This field contains a 16-bit counter that increments for	--	RO
	Counter	each symbol error. The counter stops when full (and		SC
		does not roll over) and self-clears on read.		SC
		does not roll over) and self-clears on read.
		In a frame with a bad symbol, each sequential six bad
		symbols count as one.

7.2.3.6Register 23: 100BASE-TX Receive Premature End of Frame Error Counter Bit Definitions

Bit(s)	Name	Description	Default	R/W


15:0	Premature End of	This field contains a 16-bit counter that increments for	--	RO
	Frame	each premature end of frame event. The counter		SC
		stops when full (and does not roll over) and self-clears		SC
		stops when full (and does not roll over) and self-clears
		on read.
		A frame without a “TR” at the end is considered a
		premature end of frame event.

7.2.3.7Register 24: 10BASE-T Receive End of Frame Error Counter Bit Definitions

Bit(s)	Name	Description	Default	R/W


15:0	End of Frame	This is a 16-bit counter that increments for each end	--	RO
	Counter	of frame error event. The counter stops when full (and		SC
		does not roll over) and self-clears on read.		SC
		does not roll over) and self-clears on read.

7.2.3.8Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions

Bit(s)	Name	Description	Default	R/W


15:0	Jabber Detect	This is a 16-bit counter that increments for each	--	RO
	Counter	jabber detection event. The counter stops when full		SC
		(and does not roll over) and self-clears on read.		SC
		(and does not roll over) and self-clears on read.

7.2.3.9Register 27: 82555 Special Control Bit Definitions

Bit(s)	Name		Description		Default	R/W


15:3	Reserved	These bits are reserved and should be set to 0b.			0	RW

2:0	LED Switch	Value	ACTLED	LILED	000	RW
	Control	000	Activity	Link
		000	Activity	Link
		001	Speed	Collision
		010	Speed	Link
		011	Activity	Collision
		100	Off	Off
		101	Off	On
		110	On	Off
		111	On	On

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Datasheet

Image 38

Intel 82555 manual Register 22 Receive Symbol Error Counter Bit Definitions, Actled Liled

Contents

Product Features 82555 10/100 Mbps LAN Physical Layer Interface Networking Silicon Revision Description Contents Repeater Mode Compliance to Industry Standards IntroductionFunctional Overview Networking Silicon 100 Mbps Mode Architectural Overview 10 Mbps Mode MII TX Interface Media Independent Interface MII Yes Transmit Error From RICRepeater mode only Pin Definitions Pin Numbers and Labels Media Independent Interface MII Pins Clock PinsTwisted Pair Ethernet TPE Pins Pin Types Media Access Control/Repeater Interface Control Pins LED Pins External Bias Pins Miscellaneous Control Pins VSS Power and Ground PinsVCC 100BASE-TX Transmit Clock Generation 100BASE-TX Adapter Mode OperationSymbol 5B Symbol Code 4B Nibble Code 100BASE-TX Transmit Blocks 2 100BASE-TX Scrambler and MLT-3 Encoder Invalid NRZ to MLT-3 Encoding Diagram 3 100BASE-TX Transmit Framing Vendor Model/Type 100BASE-TX Receive BlocksTransmit Driver 100BASE-TX Collision Detection Link Integrity 100BASE-TX Link Integrity and Auto-Negotiation SolutionCombination Tx/T4 Auto-Negotiation Solution Auto-Negotiation Adapter Mode Addresses Auto 10/100 Mbps Speed Selection Networking Silicon Datasheet 10BASE-T Transmit Blocks 10BASE-T Functionality in Adapter Mode10BASE-T Transmit Clock Generation 10BASE-T Receive Blocks 10BASE-T Link Integrity 3 10BASE-T Error Detection and Reporting10BASE-T Collision Detection 10BASE-T Jabber Control Function 10BASE-T Full Duplex Networking Silicon Datasheet Connectivity Repeater ModeSpecial Repeater Features Clock Signal Example Management Data Interface MDI Frame Structure MDI Registers 0 Bits Name Description DefaultMDI Registers Transition Register 1 Status Register Bit Definitions 10BASE-T Register 2 82555 Identifier Register Bit Definitions MDI Registers 8 MDI Registers 16 Register 17 82555 Special Control Bit Definitions 100BASE-TX 150 Register 22 Receive Symbol Error Counter Bit Definitions Actled Liled Description Bit Setting TechnologyAuto-Negotiation Functionality Priority Technology Parallel Detect and Auto-Negotiation Priority Auto-Negotiation and Parallel Detect Networking Silicon Datasheet LED Descriptions Networking Silicon Datasheet Loopback Reset and Miscellaneous Test ModesReset Scrambler Bypass Test Instruction Coding Number Code Test Instruction Select Input to Tout Absolute Maximum Ratings Electrical Specifications and Timing ParametersDC Characteristics General Operating Conditions 11.3.3 100BASE-TX Voltage/Current DC Characteristics Total supply current 230 Leakage on analog pins Symbol Parameter Conditions Min Typ Max Units AC CharacteristicsMII Clock Specifications MII Timing Parameters MII Clocks AC Timing Repeater Mode Timing Parameters RXC tri-stated a Transmit Packet Timing Parameters Squelch Test Timing Parameters Jabber Timing Parameters Receive Packet Timing Parameters 11.4.8 10BASE-T Normal Link Pulse NLP Timing Parameters Auto-Negotiation Fast Link Pulse FLP Timing Parameters Reset Timing Parameters 11.4.11 X1 Clock Specifications 11.4.12 100BASE-TX Transmitter AC Specification X1 Clock Specifications Symbol Description Min Norm Max 12.0 82555 Package Information 10.0