xIntel® PXA26x Processor Family Developer’s Manual
Contents
12.6.3 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 1, 6, or 11....12-26
12.6.4 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 2, 7, or 12....12-28
12.6.5 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 3, 8, or 13....12-31
12.6.6 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 4, 9, or 14....12-33
12.6.7 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 5, 10, or 15..12-35
12.6.8 UDC Interrupt Control Register 0 (UICR0).......................................................12-37
12.6.9 UDC Interrupt Control Register 1 (UICR1).......................................................12-38
12.6.10UDC Status/Interrupt Register 0 (USIR0).........................................................12-40
12.6.11UDC Status/Interrupt Register 1 (USIR1).........................................................12-41
12.6.12UDC Frame Number High Register (UFNHR)..................................................12-43
12.6.13UDC Frame Number Low Register (UFNLR) ...................................................12-45
12.6.14UDC Byte Count Register x (UBCRx), Where x is 2, 4, 7, 9, 12, or 14............12-45
12.6.15UDC Endpoint 0 Data Register (UDDR0).........................................................12-46
12.6.16UDC Data Register x (UDDRx), Where x is 1, 6, or 11....................................12-47
12.6.17UDC Data Register x (UDDRx), Where x is 2, 7, or 12....................................12-48
12.6.18UDC Data Register x (UDDRx), Where x is 3, 8, or 13....................................12-48
12.6.19UDC Data Register x (UDDRx), Where x is 4, 9, or 14....................................12-49
12.6.20UDC Data Register x (UDDRx), Where x is 5, 10, or 15..................................12-49
12.6.21UDC Register Locations ...................................................................................12-50
13 AC97 Controller Unit...................................................................................................................13-1
13.1 Overview..........................................................................................................................13-1
13.2 Feature List.......................................... ... ............................................ .............................13-1
13.3 Signal Description................................... .... ........................................... ..........................13-2
13.3.1 Signal Configuration Steps.................................................................................13-2
13.3.2 Example AC-link.................................................................................................13-2
13.4 AC-link Digital Serial Interface Protocol...........................................................................13-3
13.4.1 AC-link Audio Output Frame (SDATA_OUT)......................................................13-4
13.4.2 AC-link Audio Input Frame (SDATA_IN).............................................................13-8
13.5 AC-link Low Power Mode...................................................................... ........................13-12
13.5.1 Powering Down the AC-link..............................................................................13-12
13.5.2 Waking up the AC-link......................................................................................13-13
13.6 ACUNIT Operation.........................................................................................................13-14
13.6.1 Initialization.......................................................................................................13-15
13.6.2 Trailing bytes....................................................................................................13-16
13.6.3 Operational Flow for Accessing Codec Registers............................................13-16
13.7 Clocks and Sampling Frequencies..................................................... ...........................13-16
13.8 Functional Description...................................................................................................13-17
13.8.1 FIFOs................................................................................................................13-17
13.8.2 Interrupts...........................................................................................................13-18
13.8.3 Registers...........................................................................................................13-18
14 Inter-Integrated Circuit Sound Controller....................................................................................14-1
14.1 Overview..........................................................................................................................14-1
14.2 Signal Descriptions....................................................................................... ...................14-2
14.3 Controller Operation........................................................................................................14-3
14.3.1 Initialization.........................................................................................................14-3
14.3.2 Disabling and Enabling Audio Replay.................................................................14-4
14.3.3 Disabling and Enabling Audio Record................................................................14-4
14.3.4 Transmit FIFO Errors..........................................................................................14-5