Intel PXA26X 7.6.2.1 Beginning-of-Line Pixel Clock Wait Count (BLW), 7.6.2.2 End-of-Line Pixel Clock Wait Count (ELW), 7.6.2.3 Horizontal Sync Pulse Width (HSW)

Intel® PXA26x Processor Family Developer’s Manual 7-29
Liquid Crystal Displa y Controller
7.6.2.1 Beginning-of-Line Pixel Clock Wait Count (BLW)
The 8-bit beginning-of-line pixel clock wait count (BLW) field specifies the number of dummy
pixel clocks to insert at the beginning of each line or row of pixels. After the line clock for the
previous line has been negated, the value in BLW is used to count the number of pixel clocks to
wait before starting to output the first set of pixels in the next lin e. BLW generates a wait period
ranging from 1 to 256 pixel clock cy c l e s. BLW must be pr og rammed with the desired number of
pixel clocks minus one. L_PCLK does not toggle during these “dummy” pixel clock cycles in
passive display mode. It does toggle continuously in active dis play mode.
7.6.2.2 End-of-Line Pixel Clock Wait Count (ELW)
The 8-bit end-of-line pixel clock wait count (ELW) fiel d specifies the number of “dummy” pixel
clocks to insert at the end of each line or row of pixels before pulsing the line clock pin. Once a
complete line of pixels is transmitted to the LCD driver, the value in ELW is used to count the
number of pixel clocks to wait before pulsing the line clock. ELW generates a wait period ranging
from 1 to 256 pixel clock cycles. ELW must be program med with the desired number of pixel
clocks minus one. L_PCLK does not toggle during these dummy pixel clock cycles in passive
display mode. It does toggle continuously in active display mo de.
7.6.2.3 Horizontal Sync Pulse Width (HSW)
Note: For this section, the term “pulse width” refers to the time which L_LCLK is asserted, rather than
the time for a cycle of the line clock to occur.
The 6-bit horizontal sync pulse width (HSW) field specifies the pulse width (minus 1) of the line
clock in passive mode or the horizontal synch ronization pulse in active mode. L_LCLK is asserted
each time a line is sent to the display and a programmable number of pixel clock wait s tates have
23:16 ELW
END-OF-LINE PIXEL CLOCK WAIT COUNT (Section 7.6.2.2):
This value (0–255) specifies the number of pixel clock periods to add to the end of a line
transmission before line clock is asserted. EOL = (ELW+1).
In passive display mode, pixel clock is held in its inactive state during the end-of-line wait
period. In active display mode, it toggles.
15:10 HSW
HORIZONTAL SYNC PULSE WIDTH (Section 7.6.2.3):
This value (0–63) specifies the number of pixel clock periods to pulse the line clock at the
end of each line. HSYNC pulse width = (HSW+1).
In passive display mode, pixel clock is held in its inactive state during the generation of the
line clock. In active display mode, it toggles.
9:0 PPL PIXELS PER LINE (Section 7.6.2.4):
Specifies the number of pixels contained within each line on the LCD display. Actual pixels
per line = (PPL+1).
Table 7-4. LCD Controller Control Register 1 (Sheet 2 of 2)
Physical Address
0x4400_0004 LCD Controller Control Register 1 LCD Controller
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BLW ELW HSW PPL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description