Intel PXA26X 6.6.2 SDRAM Mode Register Set Configuration Register

6-12 Intel® PXA26x Processor Family Developer’s Manual
Memory Controller
6.6.2 SDRAM Mode Register Set Configuration Register
The MDMRS register issues an Mode Register Set (MRS) command to the SDRAM. The value
written in this register is placed directly on address lines MA[24:17] dur ing the MRS command.
For MA[16:10], values which are fixed or derived from the MDCNFG register are placed on the
address bus. When setting the values to be written out on the address lines, base the values on the
addressing mode being used. Although writing to this register triggers an MRS command, the
corresponding chip-select values are asserted only if the memory banks are enabled via the
MDCNFG register. Therefore, to appropriately writ e a n ew MRS valu e to S DRAM, first e nabl e the
memory via the MDCNFG register, and then write the MDMRS register. Use this register solely
for generating the MRS command.
All values in the MDCNFG register must be programmed correctly to ens ure proper operation of
the device. Refer to Table 6- 4 for the bit definitions.
The MDMRS[MDBLx] bits configure the SDRAM to a burst length of four . This value is fixed and
cannot be changed. For transfer cycles that require more data than the set burst length of four, the
controller can preform as many bursts as necessary to transfer the required amount of data. For
example, during a cache line fill the controller can perform a four-beat burst followed immedia tely
by another four-beat burst. This approach requi res t he c ontro ller to g enera te the fi rst address for the
second burst. During transfer cycles less than four beats, the controlle r ignores the data it does not
need. For instance, if the SDRAM is configured as non-cache-able, single beat reads are seen on
the bus as a four-beat read with only one beat that is used by the processor. This also applies to a
single-beat write.
Table 6-4. MDMRS Register Bitmap (Sheet 1 of 2)
0x4800 0040 MDMRS processor
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
MDMRS2
MDCL2
MDADD2
MDBL2
Reserved
MDMRS0
MDCL0
MDADD0
MDBL0
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0
31 — Reserved
30:23 MDMRS2 MRS VALUE TO BE WRITTEN TO SDRAM FOR PARTITION PAIR 2.
22:20 MDCL2 SDRAM PARTITION PAIR 2 CAS LATENCY – Derived from MDCNFG:DTC2. Writes are
ignored. Ready-only.
19 MDADD2 SDRAM PARTITION PAIR 2 BURST TYPE – Fix to sequential addressing. Writes are
ignored. Always reads 0.
18:16 MDBL2 SDRAM PARTITION PAIR 2 BURST LENGTH – Fixed to a burst length of four. Writes are
ignored. Always reads 010.
15 — Reserved
14:7 MDMRS0 MRS VALUE TO BE WRITTEN TO SDRAM FOR PARTITION PAIR 0.