Intel PXA26X 8.6 Baud Rate Generation, 8.7 SSP Serial Port Registers

Intel® PXA26x Processor Family Developer’s Manual 8-7
Synchronous Serial Port Controller
8.5.1 Using Programmed I/O Data Transfers
Data words are 32 bits wide, but only 16-bit samples are transferred. Only the lower 2 bytes of a
32-bit word have valid data. The upper 2 bytes are not used and include invalid data that must be
discarded.
The processor can fill or empty FIFOs in response to an interrupt from the FIFO logic. Each FIFO
has a programmable interrupt threshold. When the threshold value is exceeded and an interrupt is
enabled, an interrupt that signals the CPU to empty the receive FIFO or refill the transmit FIFO is
generated.
The user can also poll the SSP Status Register (see Section8.7.4) to determine how many samples
are in a FIFO or whether the FIFO is full or empty.
8.5.2 Using DMA Data Transfers
The DMA controller can also be programmed to transfer data to and from the SSP’s FIFO’s. Refer
to Chapter 5, “Direct Memory Access Controller” for instructions on programming the DMA
channels.
The steps for the DMA programming model are:
1. Program the transmit/receive byte count (buffer length) and burst size.
2. Program the DMA request to channel map register for SSP.
3. Set the run bit in th e DMA control regist er.
4. Set the desired values in the SSP control registers.
5. E nable the SSP by setting the SSE bit in the SSP Control Register 0 (see Section8.7.1).
6. Wait for both the DMA transmit and receive interrupt requests.
Note: If the transmit/receive byte count is not a multipl e of the transfer burs t si ze, the user mus t check the
SSP Status Register (see Section8.7 .4) to determine if any data remains in the receive FIFO.
8.6 Baud Rate Generation
The baud (or bit-rate clock) is generated internally by dividing the internal clock (3.6864MHz).
The internal clock is first divided by 2 and this divided clock feeds a programmable divider to
generate baud rates from 7.2Kbps to 1.8432 Mbps. Setting the External Clock Select (ECS, see
Section8.7.1.3) bit to 1 enables an external clock (SSPEXTCLK) to replace the 3.6864-MHz-
standard-internal clock. The external clock is also di vided by 2 b efo re it is fed to the pr ogr amma ble
divider.
8.7 SSP Serial Port Registers
The SSPC has five registers. It has two control, one data, and one status register:
•Use the SSPC Control Registers (SSCR0 and SSCR1) to program the baud rate, data length,
frame format, data transfer mechanism, and port enabling. They also control the FIFO