Intel PXA26X 5.1.4.2 Descriptor Fetch Mode

Intel® PXA26x Processor Family Developer’s Manual 5-7
Direct Memory Access Controller
Figure 5-3. No-Descriptor Fetch Mode Channel State
5.1.4.2 Descriptor Fetch Mode
In descriptor fetch mode, the DMAC registers are loaded from DMA descriptors in main memory.
Multiple DMA descriptors can be chained together in a list. This all ows a D MA channel to t ransfer
data to and from a number of locations that are not contiguous. The descriptor’s protocol design
allows descriptors to be added efficiently to the descriptor list of a running DMA stream.
A typical descriptor fetch mode (DCSR[NODESCFETCH] = 0) operation is:
1. The channel is in an uninitialized state after reset.
2. The software writes a descriptor address (aligned to a 16-byte boundary) to the DDADR
register.
3. The software writes a 1 to the DCSR[RUN] bit.
4. The DMAC fetches t he four-word descriptor (assuming that the mem ory is already set up with
the descriptor chain) from the memory indicated by DDADR.
5. The four-word DMA descriptor, aligned on a 16-byte boundary in main memory, loads the
these registers:
— Word [0] -> DDADRx register and a single flag bit. Points to the next four-word
descriptor.
— Word [1] -> DSADRx register for the current transfer.
— Word [2] -> DTADRx register for the current transfer.
DCSR[RUN]=0,
DCSR[NODESCFETCH]=1,
DSADR,DTADR,
DCMD programmed
Uninitialized
Vali d
RESET (Hardware or Sleep)
not running
(running)
Wait
for
request Transferring Data
Stopped
descriptor Error
Channel
RUN=1
DCMD[LENGTH] 0
& DCMD[FLOWSRC] = 0
& DCMD[FLOWTRG] = 0
DDADR[STOP] = 1
DDADR[STOP] = 1
DCMD[FLOWSRC] xor
DCMD[FLOWTRG] = 1
DCMD[FLOWSRC] &
DCMD[FLOWTRG] = 0
Request Asserted
DDADR[STOP] = 0
DCMD[FLOWSRC] xor
DCMD[FLOWTRG] = 1
No
descriptor
fetch RUN=0
RUN=0
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