3-12 Intel® PXA26x Processor Fa mily Developer’s Manual
Clocks and Power Manager
Software must then shut down the system and enter sleep mode. See Section 3.4.9.3, “Entering
Sleep Mode” for more details.
3.4.7 33-MHz Idle Mode
33-MHz idle mode has the lowest pow er consumption of any idle mode . The run mode frequency
selected in the Core Clock Configuration Register (CCCR) directly affects the pro cessor id le mode
power consumption. Faster run mode frequencies consume more power. 33-MHz idle mode places
the processor a special low speed run mode before entering idle. This is simila r to n ormal idl e sin ce
the CPU core clock can be stopped during periods of processor inactivity and continue to monitor
on- and off-chip interrupt service requests. 33-MHz idle limitations are:
•Peripherals will not function correctly a nd should be disabled before entering this mode.
•A Frequency Change Sequence must be performed upon entry to and exit from 33-MHz idle
mode.
•SDRAM is placed in self refresh before entering 33-MHz idle mode, because SDRAM cannot
be refreshed correctly in 33-MHz idle mode. Carefully consider the processor interrupt
behavior when the SDRAM in self refresh. To allow the interrupts to occur while SDRAM is
in self refresh, set the I and F bits in the CPSR. This allows interrupts to wake the processor
from idle mode without jumping to the interrupt handler. When the system’s SDRAM is no
longer in self refresh, the I and F bits can be cleared and the interrupt is handled.
•Because nBATT_FAULT and nVDD_FAULT can cause a data abort interrupt, the function of
these pins in 33-MHz idle mode also needs special consideration. Either the Imprecise Data
Abort Enable (IDAE) bit in the Power Manager Control Register (PMCR) must be clear,
(causing the processor to immediately enter sleep mode if either nBATT_FAULT or
nVDD_FAULT are a sse rted) or take software precautions to avoid starting execution in or
trying to use SDRAM while it is in self refresh.
During 33-Mhz idle mode these system unit modul e s are functional:
•Real-time clock
•Operating system timer
•Interrupt controller
•General purpose I/O
•Clocks and power mana ger
•Flash ROM/SRAM
Unlike normal idle mode, in 33-MHz idle mode al l ot her per iph era l un its can not be us ed , inclu din g
SDRAM, LCD and DMA controllers.
3.4.7.1 Entering 33-MHz Idle Mode
During idle mode, the processor core clocks stop. Before the clocks stop, all critical applications
must be finished and peripherals tur ned of f. I f s oft war e i s exe cu tin g fro m SD RAM, t he l ast thre e of
the following steps must be loaded into the cache before being performed.
1. Set the I and F bits in the CPSR register to mask all interrupts
2. Place the SDRAM into self refresh mode