17-24 Intel® PXA26x Processor Family Developer’s Manual

Hardware UART
See Section17.4.2.3, “FIFO DMA Mode Operation” for details on using the DMA to receive data.Table 17-15. LSR Bit Definitions (Sheet 1 of 3)
Physical Address
0x4160_0014 Line Status Reg. (LSR) PXA26x Processor Family Hardware
UART
User
Settings
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
FIFOE
TEMT
TDRQ
BI
FE
PE
OE
DR
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 1 0 0 0 0 0
Bits Access Name Description
31:8 N/A — Reserved – Read as unknown and must be written as zero.
7RFIFOE
FIFO ERROR STATUS:
In non-FIFO mode, this bit is 0. In FIFO Mode, FIFOE is set to 1 when there
is at least one parity error, framing error, or break indication for any of the
characters in the FIFO. A processor read to the LSR does not reset this bit.
FIFOE is reset when all erroneous characters have been read from the
FIFO. If DMA requests are enabled (IER bit 7 is set to 1) and FIFOE is set
to 1, the error interrupt is generated and no receive DMA request is
generated even when the receive FIFO reaches the trigger threshold. Once
the errors have been cleared by reading the FIFO, DMA requests are re-
enabled automatically. If DMA requests are not enabled (IER bit7 is set to
0), FIFOE set to 1 does not generate an error interrupt.
0 – No FIFO or no errors in receiver FIFO
1 – At least one character in receiver FIFO has errors
6RTEMT
TRANSMITTER EMPTY:
Set when the Transmit Holding Register and the Transmitter Shift Register
are both empty. It is cleared when either the Transmit Holding Register or
the Transmitter Shift Register contains a data character. In FIFO mode,
TEMT is set when the transmitter FIFO and the Transmit Shift Register are
both empty.
0 – There is data in the Transmit Shift Register, the Transmit Holding
Register, or the FIFO
1 – All the data in the transmitter has been shifted out