Intel® PXA26x Processor Family Developer’s Manual 14-3
Inter-Integrated Circuit Sound Controller
To configure SYNC and SDATA_OUT as outputs, follow these steps:
1. Program SYSUNIT’s GPIO Direction Register (GPDR). See Section4.1.3.2, “GPIO Pin
Direction Registers (GPDR0, GPDR1, GPDR2)” on page4-9 for details regarding the GPDR.
2. Program SYSUNIT’s GPIO Alternate Function Select Register (GAFR). See Section4.1.3.6,
“GPIO Alternate Function Register (GAFR)” on page4-17 for details regarding the GAFR.
To configure SDATA_IN as an input, follow these steps:
1. Program SYSUNIT’s GPIO Direction Register (GPDR). See Section4.1.3.2, “GPIO Pin
Direction Registers (GPDR0, GPDR1, GPDR2)” on page4-9 for details regarding the GPDR.
2. Program SYSUNIT’s GPIO Alternate Function Select Register (GAFR). See Section4.1.3.6,
“GPIO Alternate Function Register (GAFR)” on page4-17 for details regarding the GAFR.
14.3 Controller Operation
The I2S Controller (I2SC) can be accessed either by the processor or by the DMA control ler.
The processor uses programmed I/O instructions to access the I2SC and can access the follow ing
types of data:
•I2SC registers data — All registers are 32 bits wide and are aligned to word boundaries. See
Section14.6, “I2S Controller Register Descriptions” for further details.
•I2SC FIFO data — An entry is placed into the transmit FIFO by writing to the I2SC’s Serial
Audio Data register (SADR). Writing to SADR updates a transm it FI FO ent ry. Reading SADR
flushes out a receive FIFO entry.
•I2S CODEC data — The CODEC registers can be accessed through the L3 bus. The L3 bus
operation is emulated by software controlling 3 GPIO pins .
The DMA controller can only access the FIFOs. Accesses are made through the data registers, as
explained in the previous paragraph. The DMA controller accesses FIFO data in blocks of 8, 16, or
32 bytes. The DMA controller responds to the foll owing DMA requests made by the I2SC:
•The transmit FIFO request is based on the transmit threshold (TFTH) setting and is asserted if
the transmit FIFO has less than TFTH+1 entries. See Table14-3, “SACR0 Bit Descriptions”
on page14-8 for further details regarding TFTH.
•The receive FIFO request is based on the receive threshold (RFTH) setting and is asserted if
the receive FIFO has RFTH+1 or more entries. See Table14-3, “SACR0 Bit Descriptions” on
page14-8 for f urther details regarding RFTH.

14.3.1 Initialization

1. Set the BITCLK direction by programming the SYSUNIT’s GPIO Direction register, the
SYSUNIT’s GPIO Alternate Function Sele ct register, and the I2SC’s Serial Audio Controller
Global Control register (bit 2).
2. Choose between Normal I2S or MSB-Justified modes of operati on. This can be done by
programming bit 0 of Serial Audio Controller I2S/MSB-Justified Control Register (SACR1).
For further details, see Section14.6.2, “Serial Audio Controller I2S/MSB-Justified Control
Register (SACR1)” on page14-10.