Intel PXA26X 12.3 Universal Serial Bus Protocol

Intel® PXA26x Processor Family Developer’s Manual 12-3

Universal Serial Bus Device Controller

Data flow is relative to the USB host. IN packets represent data flow fr om the UDC to the host.

OUT packets represent data flow from the host to the UDC.

The FIFOs for the bulk and isochronous endpoints are double-buffered so one packet can be

processed as the next is assembled. While the UDC transmits an IN packet from a particular

endpoint, the core can load the same endpoint for the next frame transmission. While the core

unloads an OUT endpoint, the UDC can continue to process the next incoming packet to that

endpoint.

12.3 Universal Serial Bus Protocol

After a core reset or when the USB host issues a USB reset, the UDC configures all endpoints and

is forced to use the USB default address, zero. After the UDC configures the endpoints, the host

assigns the UDC a unique address. At this point, the UDC is unde r the host’s control and responds

to commands that use control transactions to transmit to endpoint 0.

12.3.1 Signalling Levels

USB uses differential signalling to encode data and to indicate various bus conditions. The USB

specification refers to the J and K data states to differentiate between high- and low-speed

transmissions. Because the UDC suppor ts onl y 12Mbps transmissions, references are only ma de t o

actual data state zero and actual data state 1.

By decoding the polarity of the UDC+ and UDC- pins and using differential data, four distinct

states are represented. Two of the four states represent data. A 1 indicates that UDC+ is high and

UDC- is low. A zero indicates that UDC+ is low and UDC- is high. The two remain ing states and

pairings of the four en codings are further dec oded to represent the current state of the USB.

Table12-2 shows how differential signalling represents eight different bus states.

Hosts and hubs have pu ll-down resistors on both the D+ and D- lin es. When a device is not

attached to the cable, the pull-down resistors cause D+ and D- to be pulled down below the single-

ended low threshold of the host or hub. This creates a state called single-ended zero (SE0) . The

Table 12-2. USB States

Bus State UDC+/UDC- Pin Levels

Idle UDC+ high, UDC- low (same as a 1).

Suspend Idle state for more than 3ms.

Resume UDC+ low, UDC- high (same as a 0).

Start of Packet Transition from idle to resume.

End of Packet UDC+ AND UDC- low for 2 bit times followed by an idle for 1 bit time.

Disconnect UDC+ AND UDC- below single-ended low threshold for more than 2.5µs.

(Disconnect is the static bus condition that results when no device is plugged into a hub

port.)

Connect UDC+ OR UDC- high for more than 2.5µs.

Reset UDC+ AND UDC- low for more than 2.5µs. (Reset is driven by the host controller and

sensed by a device controller.)

Contents

Main ii Intel PXA26x Processor Family D evel ope rs M an ual Contents Contents Page Page Page Page Page Page Page Page Page Figures Page Page Tables Page Page Page Page Page Page Page Page Introduction 1 1.1 Intel XScale Core Features 1.2 System Integration Features 1.2.1 Memory Controller 1.2.2 Clocks and Power Controllers 1.2.3 Universal Serial Bus (USB) Client 1.2.4 Direct Memory Access Controller (DMAC) 1.2.5 Liquid Crystal Display (LCD) Controller 1.2.6 AC97 Controller 1.2.7 Inter-Integrated Circuit Sound (I2S) Controller 1.2.8 Multimedia Card (MMC) Controller 1.2.9 Fast Infrared (FIR) Communication Port 1.2.10 Synchronous Serial Protocol Controller (SSPC) 1.2.11 Inter-Integrated Circuit (I2C) Bus Interface Unit 1.2.12 General Purpose Input/Output (GPIO) Page 1.2.20 Network Synchronous Serial Protocol Port 1.2.21 Audio Synchronous Serial Protocol Port 1.2.22 Hardware UART (HWUART) System Architecture 2 2.1 Overview 2-2 Intel PXA26x Processor Family Developers Manual 2.2 Package Types Figure 2-1. Block Diagram 2.3 Intel XScale Microarchitecture Implementation Options 2.3.1 CPU Core Fault Register PSFS Bit 2.3.2 Coprocessor 14 Registers 0-3 Performance Monitoring 2.3.3 Coprocessor 14 Register 6 and 7 Clock and Powe r Management 2.3.4 Coprocessor 15 Register 0 ID Register Definition 2.3.5 Coprocessor 15 Register 1 P-Bit 2.4 Input/Output Ordering 2.5 Semaphores 2.6 Interrupts 2.7 Reset 2.8 Internal Registers 2.9 Selecting Peripherals vs. General Purpose Input/ Output 2.10 Power on Reset and Boot Operation 2.11 Power Management 2.12 Pin List 2-10 Intel PXA26x Processor Family Developers Manual Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 2 of 12) Intel PXA26x Processor Family Developers Manual 2-11 Table 2-6. Pin & Signal Descriptions for the PXA26x P r oc essor Family (Sheet 3 of 12) 2-12 Intel PXA26x Processor Family Developers Manual Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 4 of 12) Intel PXA26x Processor Family Developers Manual 2-13 Table 2-6. Pin & Signal Descriptions for the PXA26x P r oc essor Family (Sheet 5 of 12) 2-14 Intel PXA26x Processor Family Developers Manual Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 6 of 12) Intel PXA26x Processor Family Developers Manual 2-15 Table 2-6. Pin & Signal Descriptions for the PXA26x P r oc essor Family (Sheet 7 of 12) 2-16 Intel PXA26x Processor Family Developers Manual Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 8 of 12) Intel PXA26x Processor Family Developers Manual 2-17 Table 2-6. Pin & Signal Descriptions for the PXA26x P r oc essor Family (Sheet 9 of 12) 2-18 Intel PXA26x Processor Family Developers Manual Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 10 of 12) Intel PXA26x Processor Family Developers Manual 2-19 Table 2-6. Pin & Signal Descriptions for the PXA26x P r oc essor Family (Sheet 11 of 12) 2-20 Intel PXA26x Processor Family Developers Manual Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 12 of 12) Intel PXA26x Processor Family Developers Manual 2-21 2.13 Register Address Summary Tabl e 2-8 lists the registers p resent in the PXA26x processor family. Table 2-7. Pin Description Notes Table 2-8. Register Address Summary (Sheet 1 of 13) 2-22 Intel PXA26x Processor Family Developers Manual Table 2-8. Register Address Summary (Sheet 2 of 13) Intel PXA26x Processor Family Developers Manual 2-23 Table 2-8. Register Address Summary (Sheet 3 of 13) 2-24 Intel PXA26x Processor Family Developers Manual Table 2-8. Register Address Summary (Sheet 4 of 13) Intel PXA26x Processor Family Developers Manual 2-25 Table 2-8. Register Address Summary (Sheet 5 of 13) 2-26 Intel PXA26x Processor Family Developers Manual Table 2-8. Register Address Summary (Sheet 6 of 13) Intel PXA26x Processor Family Developers Manual 2-27 Table 2-8. Register Address Summary (Sheet 7 of 13) 2-28 Intel PXA26x Processor Family Developers Manual Table 2-8. Register Address Summary (Sheet 8 of 13) Intel PXA26x Processor Family Developers Manual 2-29 Table 2-8. Register Address Summary (Sheet 9 of 13) 2-30 Intel PXA26x Processor Family Developers Manual Table 2-8. Register Address Summary (Sheet 10 of 13 ) Intel PXA26x Processor Family Developers Manual 2-31 Table 2-8. Register Address Summary (S heet 11 of 13) 2-32 Intel PXA26x Processor Family Developers Manual Table 2-8. Register Address Summary (Sheet 12 of 13 ) 2.14 Memory Map 2-34 Intel PXA26x Processor Family Developers Manual Figure 2-2. Memory Map (Part One) From 0x8000 0000 to 0xFFFF FFFF Figure 2-3. Memory Map (Part Two) From 0x0000 0000 to 0x7FFF FFFF Page Clocks and Power Manager 3 3.1 Clock Manager Introduction 3.2 Power Manager Introduction 3.3 Clock Manager Page 3.3.1 32.768-KHz Oscillator 3.3.2 3.6864-MHz Oscillator 3.3.3 Core Phase Locked Loop Intel PXA26x Processor Family Developers Manua l 3-5 3.3.4 95.85-MHz Peripheral Phase Locked Loop Table 3-1. Core PLL Output Frequencies for 3.6864-MHz Crystal Table 3-2. 95.85-MHz Peripheral PLL Output Frequencies for 3.6864-MHz Crystal 3.3.5 147.46-MHz Peripheral Phase Locked Loop 3.3.6 Clock Gating 3.4 Resets and Power Modes 3.4.1 Hardware Reset 3.4.1.1 Invoking Hardware Reset 3.4.1.2 Behavior During Hardware Reset 3.4.1.3 Completing Hardware Reset 3.4.2 Watchdog Reset 3.4.3 GPIO Reset 3.4.3.1 Invoking GPIO Reset 3.4.3.2 Behavior During GPIO Reset 3.4.3.3 Completing GPIO Reset 3.4.4 Run Mode 3.4.5 Turbo Mode 3.4.5.1 Entering Turbo Mode 3.4.5.2 Behavior in Turbo Mode 3.4.5.3 Exiting Turbo Mode 3.4.6 Idle Mode 3.4.6.1 Entering Idle Mode 3.4.6.2 Behavior in Idle Mode 3.4.6.3 Exiting Idle Mode 3.4.7 33-MHz Idle Mode 3.4.7.2 Behavior in 33-MHz Idle Mode 3.4.7.3 Exiting 33-MHz Idle Mode 3.4.8 Frequency Change Sequence 3.4.8.1 Preparing for the Frequency Change Sequence 3.4.8.2 Starting the Frequency Change Sequence 3.4.8.3 Behavior During the Frequency Change Sequence 3.4.8.4 Completing the Frequency Change Sequence 3.4.9 Sleep Mode 3.4.9.1 Sleep Mode External Voltage Regulator Requirements 3.4.9.2 Preparing for Sleep Mode 3.4.9.3 Entering Sleep Mode 3.4.9.4 Behavior in Sleep Mode 3.4.9.5 Exiting Sleep Mode 3.4.10 Power Mode Summary Intel PXA26x Processor Family Developers Manua l 3-21 Table 3-5. Power Mode Exit Sequence Table 3-22 Intel PXA26x Processor Fa mily Developers Manual 3.5 Power Manager Registers This section describes the 32-bit registers that control the power manager. Table 3-6. Power and Clock Supply Sources and States During Power Modes 3.5.1 Power Manager Control Register (PMCR) 3.5.2 Power Manager General Configuration Register (PCFR) 3.5.3 Power Manager Wake-Up Enable Register (PWER) 3.5.4 Power Manager Rising-Edge Detect Enable Register (PRER) 3.5.5 Power Manager Falling-Edge Detect Enable Register (PFER) 3.5.6 Power Manager GPIO Edge Detect Status Register (PEDR) 3.5.7 Power Manager Sleep Status Register (PSSR) 3-30 Intel PXA26x Processor Fa mily Developers Manual 3.5.8 Power Manager Scratch Pad Register (PSPR) Table 3-13. PSSR Bit Definitions (Sheet 2 of 2) Table 3-14. PSPR Bit Definitions 3.5.9 Power Manager Fast Sleep Wake Up Configuration Register (PMFWR) 3.5.10 Power Manager GPIO Sleep State Registers (PGSR0, PGSR1, PGSR2) 3-32 Intel PXA26x Processor Fa mily Developers Manual Table 3-16. PGSR0 Bit Definitions Table 3-17. PGSR1 Bit Definitions Table 3-18. PSPR Bit Definitions 3.5.11 Reset Controller Status Register (RCSR) 3-34 Intel PXA26x Processor Fa mily Developers Manual 3.5.12 Power Manager Register Locations Table 3-19. RCSR Bit Definitions Table 3-20. Power Manager Register Locations (Sheet 1 of 2) 3.6 Clocks Manager Registers 3.6.1 Core Clock Configuration Register (CCCR) 3-36 Intel PXA26x Processor Fa mily Developers Manual Table 3-21. CCCR Register Bi tma p an d Bit Definitions Intel PXA26x Processor Family Developers Manua l 3-37 3.6.2 Clock Enable Register (CKEN) 3-38 Intel PXA26x Processor Fa mily Developers Manual Table 3-22. CKEN Register Bitmap and Bit Definitions (Sheet 2 of 2) 3.6.3 Oscillator Configuration Register (OSCC) 3.6.4 Clocks Manager Register Locations 3.7 Coprocessor 14: Clock and Power Management 3.7.1 Core Clock Configuration Register (CCLKCFG) 3.7.2 Power Mode Register (PWRMODE) 3.8 External Hardware Considerations 3.8.1 Power-On-Reset Considerations 3.8.2 Driving the Crystal Pins from an External Clock Source 3.8.3 Noise Coupling Between Driven Crystal Pins and a Crystal Oscillator System Integration Unit 4 4.1 General-Purpose Input/Output 4.1.1 GPIO Operation Page 4.1.2 GPIO Alternate Functions 4-4 Intel PXA26x Processor Family Developers Manual Table 4-1. GPIO Alternate Functions (Sheet 2 of 5) Intel PXA26x Processor Family Developers Manual 4-5 Table 4-1. GPIO Alternate Functions (Sheet 3 of 5) 4-6 Intel PXA26x Processor Family Developers Manual Table 4-1. GPIO Alternate Functions (Sheet 4 of 5) 4.1.3 GPIO Register Definitions 4.1.3.1 GPIO Pin-Level Registers (GPLR0, GPLR1, GPLR2) Intel PXA26x Processor Family Developers Manual 4-9 This is read/write register. Ignore reads from reserved bits. Write zer os to reserved bits. 4.1.3.2 GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2) Table 4-4. GPLR1 Bit Definitions Table 4-5. GPLR2 Register Bitmap 4-10 Intel PXA26x Processor Family Developers Manual Table 4-6. GPDR0 Bit Defin itions Table 4-7. GPDR1 Bit Defin itions Table 4-8. GPDR2 Register Bitmap Intel PXA26x Processor Family Developers Manual 4-11 Table 4-10. GPSR1 Bit Definitions 4-12 Intel PXA26x Processor Family Developers Manual Table 4-11. GPSR 2 Re g i ster Bitmap Table 4-12. GPCR0 Bit Definitions Table 4-13. GPCR1 Bit Definitions Page 4-14 Intel PXA26x Processor Family Developers Manual Table 4-16. GRER1 Bit Definitions Table 4-17. GRER2 Register Bitmap Intel PXA26x Processor Family Developers Manual 4-15 Table 4-18. GFER0 Bit Definitions Table 4-19. GFER1 Bit Definitions Table 4-20. GFER2 Register Bitmap 4.1.3.5 GPIO Edge Detect Status Register (GEDR) Intel PXA26x Processor Family Developers Manual 4-17 4.1.3.6 GPIO Alternate Function Register (GAFR) Table 4-22. GEDR1 Bit Definitions Table 4-23. GEDR2 Register Bitmap Page Intel PXA26x Processor Family Developers Manual 4-19 Table 4-26. GAFR1_L Bit Definitions Table 4-27. GAFR1_U Bit Definitions 4-20 Intel PXA26x Processor Family Developers Manual Table 4-28. GAFR2_L Bit Definitions Table 4-29. GAFR2_U Register Bitmap 4.1.3.7 Example Procedure for Configuring the Alternate Function Registers 4.1.4 GPIO Register Locations 4-22 Intel PXA26x Processor Family Developers Manual 4.2 Interrupt Controller Table 4-30. GPIO Register Addresses (Sheet 2 of 2) 4.2.1 Interrupt Controller Operation 4.2.2 Interrupt Controller Register Definitions 4.2.2.1 Interrupt Controller Mask Register (ICMR) Intel PXA26x Processor Family Developers Manual 4-25 4.2.2.2 Interrupt Controller Level Register (ICLR) Table 4-31. ICMR Register Bitmap Table 4-32. ICLR Register Bitmap 4.2.2.3 Interrupt Controller Control Register (ICCR) 4.2.2.4 Interrupt Controller IRQ Pending Register (ICIP) and FIQ Pending Register (ICFP) Intel PXA26x Processor Family Developers Manual 4-27 4.2.2.5 Interrupt Controller Pending Register (ICPR) Table 4-34. ICIP Register Bitmap Table 4-35. ICFP Register Bitmap 4-28 Intel PXA26x Processor Family Developers Manual Table 4-36. ICPR Register Bitmap (Sheet 1 of 3) Intel PXA26x Processor Family Developers Manual 4-29 Table 4-36. ICPR Register Bitmap (Sheet 2 of 3) 4-30 Intel PXA26x Processor Family Developers Manual Table 4-37. List of FirstLevel Interrupts (Sheet 1 of 2) Table 4-36. ICPR Register Bitmap (Sheet 3 of 3) 4.2.3 Interrupt Controller Register Locations 4.3 Real-Time Clock (RTC) 4.3.1 Real-Time Clock Operation 4.3.2 Real-Time Clock Register Definitions 4.3.2.1 Real-Time Clock Trim Register (RTTR) 4.3.2.2 Real-Time Clock Alarm Register (RTAR) 4.3.2.3 Real-Time Clock Counter Register (RCNR) 4.3.2.4 Real-Time Clock Status Register (RTSR) 4.3.3 Trim Procedure 4.3.3.1 Oscillator Frequency Calibration 4.3.3.2 RTTR Value Calculations 4.3.3.2.1 Trim Example #1 Measured Value Has No Fractional Component 32768 4.3.4 Real-Time Clock Register Locations 4.4 Operating System Timer 4.4.1 Watchdog Timer Operation 4.4.2 Operating System Timer Register Definitions 4.4.2.1 Operating System Timer Match Register 0-3 (OSMR0, OSMR1, OSMR2, OSMR3) 4.4.2.2 Operating System Timer Interrupt Enable Register (OIER) 4-40 Intel PXA26x Processor Family Developers Manual 4.4.2.3 Operating System Timer Watchdog Match Enable Register (OWER) Table 4-45. OIER Bit Definitions Table 4-46. OWER Bit Def in i tions 4.4.2.4 Operating System Timer Count Register (OSCR) 4.4.2.5 Operating System Timer Status Register (OSSR) 4-42 Intel PXA26x Processor Family Developers Manual 4.4.3 Operating System Timer Register Locations Table 4-48. OSSR Bit Definitions Table 4-49. OS Timer Register Locations 4.5 Pulse Width Modulator 4.5.1 Pulse Width Modulator Operation 4.5.1.1 Interdependencies 4.5.2 Register Descriptions 4.5.2.1 PWM Control Registers (PWM_CTRLn) 4.5.2.2 PWM Duty Cycle Registers (PWM_DUTYn) 4.5.2.3 PWM Period Control Register (PWM_PERVALn) 4.5.3 Pulse Width Modulator Output Wave Example PWM_DUTYn = 6 PWM_PERVALn = 10 (+1) 4.5.4 Register Summary Page Page Direct Memory Access Controller 5 5.1 Direct Memory Access Description 5.1.1 Direct Memory Access Controller Channels Memory Controller DMA Controller (external) (internal) 5.1.2 Signal Descriptions 5.1.2.1 DREQ[1:0] and PREQ[37:0] Signals 5.1.2.2 DMA_IRQ Signal 5.1.3 Direct Memory Access Channel Priority Scheme Page 5.1.4 Direct Memory Access Descriptors 5.1.4.1 No-Descriptor Fetch Mode 5.1.4.2 Descriptor Fetch Mode Page 5.1.4.3 Servicing an Interrupt 5.1.5 Channel States 5.1.6 Read and Write Order 5.1.7 Byte Transfer Order 5.1.8 Trailing Bytes 5.2 Transferring Data 5.2.1 Servicing Internal Peri pherals 5.2.2 Quick Reference for Direct Memory Access Progr amming 5-14 Intel PXA26x Processor Family Developers Manual 5.2.3 Servicing Companion Chips and External Peripherals Table 5-5. DMA Quick Reference for Internal Peripherals (Sheet 2 of 2) Page 5.2.4 Memory-to-Memory Moves 5.3 Direct Memory Access Controller Registers 5.3.1 DMA Interrupt Register 5.3.2 DMA Channel Control/Status Register 5-18 Intel PXA26x Processor Family Developers Manual Table 5-7. DMA Channel Control/Status Register Bitmap and Bit Definitions (Sheet 1 of 2) Intel PXA26x Processor Family Developers Manual 5-19 5.3.3 DMA Request to Channel Map Registers Table 5-7. DMA Channel Control/Status Register Bitmap and Bit Definitions (Sheet 2 of 2) 5.3.4 DMA Descriptor Address Registers 5.3.5 DMA Source Address Registers 5.3.6 DMA Target Address Registers 5.3.7 DMA Command Registers 5-24 Intel PXA26x Processor Family Developers Manual Table 5-12. DCMDx Register Bitmap and Bit Definitions (Sheet 1 of 2) Intel PXA26x Processor Family Developers Manual 5-25 5.4 Examples This section contains examples that show how to: Table 5-12. DCMDx Register Bitmap and Bit Defini tions (Sheet 2 of 2) Page Page 5-28 Intel PXA26x Processor Family Developers Manual 5.5 Direct Memory Access Controller Registers Locations Intel PXA26x Processor Family Developers Manual 5-29 Table 5-13. DMA Controller Registers (Sheet 2 of 4) 5-30 Intel PXA26x Processor Family Developers Manual Table 5-13. DMA Controller Registers (Sheet 3 of 4) Intel PXA26x Processor Family Developers Manual 5-31 Table 5-13. DMA Controller Registers (Sheet 4 of 4) Page Memory Controller 6 6.1 Overview 6-2 Intel PXA26x Processor Family Developers Manual Figure 6-1. General Memory Interface Configuration 6.2 Functional Description 6.2.1 SDRAM Interface Overview 6.2.2 Static Memory Interface / Variable Latency I/O Interface 6.2.3 16-Bit PC Card / Compact Flash Interface 6.3 Memory System Examples Intel PXA26x Processor Family Developers Manual 6-5 Figure 6-2. SDRAM Memory System Example 6-6 Intel PXA26x Processor Family Developers Manual Figure 6-3. Asynchronous Static Memory System Example 6.4 Memory Accesses 6.4.1 Reads and Writes 6.4.2 Aborts and Nonexistent Memory 6.5 Memory Configuration Registers Intel PXA26x Processor Family Developers Manual 6-9 6.6 Synchronous DRAM Memory Interface 6.6.1 SDRAM MDCNFG Register 6-10 Intel PXA26x Processor Family Developers Manual Table 6-3. MDCNFG Register Bitmap and Bit Definitions (Sheet 2 of 3) Intel PXA26x Processor Family Developers Manual 6-11 Table 6-3. MDCNFG Register Bitmap and Bit Definiti ons (Sheet 3 of 3) 6.6.2 SDRAM Mode Register Set Configuration Register 6.6.2.1 Low-Power SDRAM Mode Register Set Configuration Register 6.6.3 SDRAM MDREFR Register Intel PXA26x Processor Family Developers Manual 6-15 Refer to Table 6- 6. Table 6-6. MDREFR Register Bitmap (Sheet 1 of 3) 6-16 Intel PXA26x Processor Family Developers Manual Table 6-6. MDREFR Regist er Bitmap (Sheet 2 of 3) Intel PXA26x Processor Family Developers Manual 6-17 6.6.4 SDRAM Memory Options Table 6-6. MDREFR Register Bitmap (Sheet 3 of 3) 6.6.4.1 SDRAM Addressing Modes Page 6-20 Intel PXA26x Processor Family Developers Manual Table 6-8. External to Internal Address Mapping for Normal Bank Addressing (Sheet 2 of 2) Intel PXA26x Processor Family Developers Manual 6-21 Table 6-9. External to Internal Address Mapping for SA-1111 Addressing (Sheet 1 of 2) 6-22 Intel PXA26x Processor Family Developers Manual Table 6-9 . Exte rnal to Inter n al Add ress Ma pping f or SA-1111 Addre s sing ( Sheet 2 of 2) Table 6-10. Pin Mapping to SDRAM Devices with Normal Bank Addressing (Sheet 1 of 3) Intel PXA26x Processor Family Developers Manual 6-23 Table 6-10. Pin Mapping to SDRAM Devices with Normal Ba n k A ddressing (Sheet 2 of 3) 6-24 Intel PXA26x Processor Family Developers Manual Table 6-11. Pin Mapping to SDRAM Devices with SA-1111 Addressing (Sheet 1 of 2) Table 6-10. Pin Mapping to SDRAM Devices with Normal Bank Addressing (Sheet 3 of 3) 6.6.5 SDRAM Command Overview Intel PXA26x Processor Family Developers Manual 6-27 6.6.6 SDRAM Waveforms Figure 6-6. SDRAM Read With a Second Re ad to Sa me B an k , Same Row 6-28 Intel PXA26x Processor Family Developers Manual Figure 6-7. SDRAM Read With a Second Read to Same Bank, Different Row Figure 6-8. SDRAM Read With a Second Read to a Different Bank Intel PXA26x Processor Family Developers Manual 6-29 Figure 6-9. SDRAM Write Figure 6-10. SDRAM Write With a Second Write to Same Bank, Same Row 6.7 Synchronous Static Memory Interface 6.7.1 Synchronous Static Memory Configuration Register Intel PXA26x Processor Family Developers Manual 6-31 Table 6-14. SXCNFG Register Bitmap (Sheet 2 of 6) 6-32 Intel PXA26x Processor Family Developers Manual Table 6-14. SXCNFG Reg ister Bitmap (Sheet 3 of 6) Intel PXA26x Processor Family Developers Manual 6-33 Table 6-14. SXCNFG Register Bitmap (Sheet 4 of 6) 6-34 Intel PXA26x Processor Family Developers Manual Table 6-14. SXCNFG Reg ister Bitmap (Sheet 5 of 6) Intel PXA26x Processor Family Developers Manual 6-35 6.7.1.1 SMROM Memory Options Table 6-14. SXCNFG Register Bitmap (Sheet 6 of 6) Table 6-16. Synchronous Static Memory External to Internal Address Mapping Options (Sheet 1 of 2) 6.7.2 Synchronous Static Memory Mode Register Set Configuration Register 6.7.3 Synchronous Static Memory Timing Diagrams 6.7.4 Non-SDRAM Timing SXMEM Operation Intel PXA26x Processor Family Developers Manual 6-39 Table 6-18. Read Configuration Register Programming Values Table 6-19. Frequency Code Configuration Values Based on Cl ock Speed (Sheet 1 of 2) 6.7.4.1 Non-SDRAM Timing Flash Read Timing Diagram 6.8 Asynchronous Static Memory 6.8.1 Static Memory Interface Page Intel PXA26x Processor Family Developers Manual 6-43 Table 6-22. 32-Bit Byte Address Bits MA[1:0] for Rea ds Based on DQM[3:0] Table 6-23. 16-Bit Byte Address Bit MA[0] for Reads Ba sed on DQM[1:0] Table 6-24. SA-1111 Register Bit Definitions 6.8.2 Asynchronous Static Memory Control Registers (MSC0 2) Intel PXA26x Processor Family Developers Manual 6-45 Table 6-25. MSC0/1/2 Register Bit Definitions ( Sheet 1 of 3) 6-46 Intel PXA26x Processor Family Developers Manual Table 6-25. MSC0/1/2 Register Bit Definitions (She et 2 o f 3) Tabl e 6-26 provides a comparison of supported Asynchronous Static Memory types. Intel PXA26x Processor Family Developers Manual 6-47 Table 6-25. MSC0/1/2 Register Bit Definitions ( Sheet 3 of 3) Table 6-26. Asynchronous Static Memory and Variable Latency I/O Capabilities (Sheet 1 of 2) 6-48 Intel PXA26x Processor Family Developers Manual 6.8.3 ROM Interface The timings for burst and non-burst ROMs are shown in Figure6-14, Figure 6-15, and Figure6-16. 6.8.3.1 ROM Timing Diagrams and Parameters Table 6-26. Asynchronous Static Memory and Variable Latency I/O Capabilities (Sheet 2 of 2) Page 6-50 Intel PXA26x Processor Family Developers Manual 6.8.4 SRAM Interface Overview 6.8.4.1 SRAM Timing Diagrams and Parameters 6.8.5 Variable Latency I/O (VLIO) Interface Overview 6.8.5.1 Variable Latency I/O Timing Diagrams and Parameters Page Page 6.8.6 FLASH Memory Interface 6.9 16-Bit PC Card/Compact Flash Interface 6.9.1 Expansion Memory Timing Configuration Register Intel PXA26x Processor Family Developers Manual 6-59 Table 6-29. MCIOx Register Bitmap Table 6-28. MCATTx Register Bitmap Table 6-30. Card Interface Command Assertion Code Table 6-60 Intel PXA26x Processor Family Developers Manual 6.9.2 Expansion Memory Configuration Register (MECR) 6.9.3 16-Bit PC Card Overview Page Page 6.9.4 External Logic for 16-Bit PC Card Implementation Intel PXA26x Processor Family Developers Manual 6-65 Figure 6-25. Expansion Card External Logic for a One-Socket Configuration 6-66 Intel PXA26x Processor Family Developers Manual Figure 6-26. Expansion Card External Logic for a Two-Socket Configuration PXA26x Processor Family Socket 1 Socket 0 6.9.5 Expansion Card Interface Timing Diagrams and Parameters 6.10 Companion Chip Interface Intel PXA26x Processor Family Developers Manual 6-69 Figure 6-29. Alternate Bus M as ter Mode Figure 6-30. Variable Latency IO 6.10.1 Alternate Bus Master Mode 6.10.1.1 GPIO Reset 6.10.1.2 nVDD_FAULT/ n BATT_FAULT with PMCR[IDAE] Disabled 6.10.1.3 nVDD_FAULT/nBATT_FAULT with PMCR[IDAE] Enabled 6.11 Options and Settings for Boot Memory 6.11.1 Alternate Booting 6.11.2 Boot Time Defaults 6.11.2.1 BOOT_DEF Read-Only Register (BOOT_DEF) Intel PXA26x Processor Family Developers Manual 6-73 6.11.2.2 Boot-Time Configurations 6-74 Intel PXA26x Processor Family Developers Manual Figure 6-32. SMROM Boot Time Configurations and Register Defaults Intel PXA26x Processor Family Developers Manual 6-75 Figure 6-33. SMROM Boot Time Configurations and Register Defaults (Continued) 6.11.3 Memory Interface Reset and Initialization 6.12 Hardware, Watchdog, or Sleep Reset Operation Page 6.13 General Purpose Input/Output Reset Procedure Liquid Crystal Display Controller 7 7.1 Overview 7.1.1 Features Intel PXA26x Processor Family Developers Manual 7-3 Figure 7-1. LCD Controller Block Diagram 7.1.2 Pin Descriptions 7.2 Liquid Crystal Display Controller Operation 7.2.1 Enabling the Controller 7.2.2 Disabling the Controller 7.2.3 Resetting the Controller 7.3 Detailed Module Descriptions 7.3.1 Input FIFOs 7.3.2 Lookup Palette 7.3.3 Temporal Modulated Energy Distribution (TMED) Dithering Page Page 7.3.4 Output FIFOs 7.3.5 Liquid Crystal Display Controller Pin Usage 7.3.5.2 Active-Display Timing 7.3.5.3 Pixel Data Pins (L_DDx) 7.3.6 Direct Memory Access 7.4 Liquid Crystal Display External Palette and Frame Buffers 7.4.1 External-Palette Buffer 7.4.2 External-Frame Buffe r Intel PXA26x Processor Family Developers Manual 7-13 Figure 7-7. 2-Bits Per Pixel Data Memory Organization Figure 7-8. 4-Bits Per Pixel Data Memory Organization Figure 7-9. 8-Bits Per Pixel Data Memory Organization Figure 7-10. 16-Bits Per Pixel Data Memory Organization Passive Mode FrameBufferSize = 16*640*480/8 = 614,400 bytes 7.5 Functional Timing FrameBufferSize --------------------------------------------------------------------------= Liquid Crystal Display Controller Figure 7-12. Passive Mode Start-of-Frame Timing Page Liquid Crystal Display Controller Figure 7-15. Active Mode Timing 7.6 Liquid Crystal Display Register Descriptions 7.6.1 LCD Controller Control Register 0 (LCCR0) Intel PXA26x Processor Family Developers Manual 7-21 Table 7-2. LCD Controller Control Register 0 (Sheet 2 of 3) 7.6.1.1 LCD Output Fifo Underrun Mask (OUM) 7.6.1.2 Branch Mask (BM) 7.6.1.3 Palette DMA Request Delay (PDD) 7.6.1.4 LCD Quick Disable Interrupt Mask (QDM) 7.6.1.5 LCD Disable (DIS) 7.6.1.6 Double-Pixel Data (DPD) Pin Mode 7.6.1.7 Passive/Active Display Select (PAS) 7.6.1.8 End of Frame Mask (EFM) 7.6.1.9 Input Fifo Underrun Mask (IUM) 7.6.1.10 Start Of Frame Mask (SFM) 7.6.1.11 LCD Disable Done Interrupt Mask (LDM) 7.6.1.12 Single-/Dual-Panel Select (SDS) Intel PXA26x Processor Family Developers Manual 7-27 7.6.1.13 Color/Monochrome Select (CMS) Figure 7-18. LCD Data-Pin Pixel Ordering 7.6.1.14 LCD Enable (ENB) 7.6.2 LCD Controller Control Register 1 (LCCR1) 7.6.2.1 Beginning-of-Line Pixel Clock Wait Count (BLW) 7.6.2.2 End-of-Line Pixel Clock Wait Count (ELW) 7.6.2.3 Horizontal Sync Pulse Width (HSW) 7.6.2.4 Pixels Per Line (PPL) 7.6.3 LCD Controller Control Register 2 (LCCR2) 7.6.3.1 Beginning-of-Frame Line Clock Wait Count (BFW) 7.6.3.2 End-of-Frame Line Clock Wait Count (EFW) 7.6.3.3 Vertical Sync Pulse Width (VSW) 7.6.3.4 Lines Per Panel (LPP) 7.6.4 LCD Controller Control Register 3 (LCCR3) 7.6.4.1 Double Pixel Clock (DPC) 7.6.4.2 Bits Per Pixel (BPP) 7.6.4.3 Output Enable Polarity (O EP) 7.6.4.4 Pixel Clock Polarity (PCP) 7.6.4.5 Horizontal Sync Polarity (HSP ) 7.6.4.6 Vertical Sync Polarity (VSP) 7.6.4.7 AC Bias Pin Transitions Per Interrupt (API) 7.6.4.8 AC Bias Pin Frequency (ACB) 7.6.4.9 Pixel Clock Divider (PCD) 7.6.5 LCD Controller DMA 7.6.5.1 Frame Descriptors 7.6.5.2 LCD DMA Frame Descriptor Address Registers (FDADRx) 7.6.5.3 LCD DMA Frame Source Address Registers (FSADRx) 7.6.5.4 LCD DMA Frame ID Registers (FIDRx) 7.6.5.5 LCD DMA Command Registers (LDCMDx) 7.6.5.5.1 Load Palette (PAL) 7.6.5.5.2 Start Of Frame Interrupt (SOFINT) 7.6.5.5.3 End Of Frame Interrupt (EOFINT) 7.6.5.5.4 Transfer Length (LEN) 7.6.6 LCD DMA Frame Branch Registers (FBRx) 7.6.7 LCD Controller Status Register (LCSR) Intel PXA26x Processor Family Developers Manual 7-43 Table 7-12. LCD Controller Status Register (Sheet 1 of 2) 7.6.7.1 Subsequent Interrupt Status (SINT) 7.6.7.2 Branch Status (BS) 7.6.7.3 End Of Frame Status (EOF) 7.6.7.4 LCD Quick Disable Status (QD) 7.6.7.5 Output FIFO Underrun Status (OU) 7.6.7.6 Input FIFO Underrun Upper Panel Status (IUU) 7.6.7.7 Input FIFO Underrun Lower Panel Status (IUL) 7.6.7.8 AC Bias Count Status (ABC) 7.6.8 LCD Controller Interrupt ID Register (LIIDR) 7.6.9 TMED RGB Seed Register 7.6.10 TMED Control Register (TCR) 7.6.10.1 TMED Energy Distribution Select (TED) 7.6.10.2 TMED Horizontal Beat Suppression (THBS) 7.6.10.3 TMED Vertical Beat Suppression (TVBS) 7.6.10.4 TMED Frame Number Adjuster Enable (FNAME) 7.6.10.5 TMED Color Offset Adjuster Enable (COAE) 7.6.11 LCD Controller Register Summary Page Synchronous Serial Port Controller 8 8.1 Overview 8.2 Signal Description 8.2.1 External Interface to Synchronous Serial Peripherals 8.3 Functional Description 8.3.1 Data Transfer 8.4 Data Formats 8.4.1 Serial Data Formats for Transfer to/from Peripherals 8.4.1.2 SPI Format Details 8.4.1.3 Microwire Format Details 8.4.2 Parallel Data Formats for FIFO Storage 8.5 FIFO Operation and Data Transfers 8.5.1 Using Programmed I/O Data Transfers 8.5.2 Using DMA Data Transfers 8.6 Baud Rate Generation 8.7 SSP Serial Port Registers 8.7.1 SSP Control Register 0 (SSCR0) Intel PXA26x Processor Family Developers Manual 8-9 Synchronous Serial Port Controller 8.7.1.1 Data Size Select (DSS) Table 8-2. SSP Control Register 0 (SSCR0) Bitmap and Bit Definitions 8.7.1.2 Frame Format (FRF) 8.7.1.3 External Clock Select (ECS) 8.7.1.4 Synchronous Serial Port Enable (SSE) 8.7.1.5 Serial Clock Rate (SCR) 8.7.2 SSP Control Register 1 (SSCR1) 8.7.2.1 Receive FIFO Interrupt Enable (RIE) 8.7.2.2 Transmit FIFO Interrupt Enable (TIE) 8.7.2.3 Loop Back Mode (LBM) 8.7.2.4 Serial Clock Polarity (SPO) 8.7.2.5 Serial Clock Phase (SPH) 8.7.2.6 Microwire Transmit Data Size (MWDS) 8.7.2.7 Transmit FIFO Interrupt/DMA Threshold (TFT) 8.7.2.8 Receive FIFO Interrupt/DMA Threshold (RFT) 8.7.3 SSP Data Register (SSDR) 8.7.4 SSP Status Register (SSSR) Intel PXA26x Processor Family Developers Manual 8-17 Synchronous Serial Port Controller 8.7.4.1 Transmit FIFO Not Full Flag (TNF) (read-only, non-interruptible) Table 8-6. SSP Status Register (SSSR) Bitmap and Bit Definitions 8.7.4.2 Receive FIFO Not Empty Flag (RNE) (read-only, non-interruptible) 8.7.4.3 SSP Busy Flag (BSY) (read-only, non-interruptible) 8.7.4.4 Transmit FIFO Service Request Flag (TFS) (read-only, maskable interrupt) 8.7.4.5 Receive FIFO Service Request Flag (RFS) (read-only, maskable interrupt) 8.7.4.6 Receiver Overrun Status (ROR) (read/write, non-maskable interrupt) 8.7.5 SSP Register Address Map Page Inter-Integrated Circuit Bus Interface Unit 9 9.1 Overview 9.2 Signal Description 9.3 Functional Description Page 9.3.1 Operational Blocks 9.3.2 Inter-Integrated Circuit Bus Interface Modes 9.3.3 Start and Stop Bus States 9.3.3.1 START Condition 9.3.3.2 No START or STOP Condition 9.3.3.3 STOP Condition 9.4 Inter-Integrated Circuit Bus Operation 9.4.1 Serial Clock Line (SCL) Generation 9.4.2 Data and Addressing Management 9.4.2.1 Addressing a Slave Device 9.4.3 Inter-Integrated Circuit Acknowledge 9.4.4 Arbitration 9.4.4.1 SCL Arbitration 9.4.4.2 SDA Arbitration 9.4.5 Master Operations 9-12 Intel PXA26x Processor Family Developers Manual Table 9-5. Master Transactions (Sheet 1 of 2) Intel PXA26x Processor Family Developers Manual 9-13 Table 9-5. Master Transactions (Sheet 2 of 2) Page Intel PXA26x Processor Family Developers Manual 9-15 9.4.6 Slave Operations Tabl e 9-6 describes ho w th e I 2C unit operates as a slave device. Table 9-6. Slave Transactions 9.4.7 General Call Address 9.5 Slave Mode Programming Examples 9.5.1 Initialize Unit 9.5.2 Write n Bytes as a Slave 9.5.3 Read n Bytes as a Slave 9.6 Master Programming Examples 9.6.1 Initialize Unit 9.6.2 Write 1 Byte as a Master 9.6.3 Read 1 Byte as a Master 9.6.4 Write 2 Bytes and Repeated Start R ead 1 Byte as a Master 9.6.5 Read 2 Bytes as a Master - Send STOP Using the Abort 9.7 Glitch Suppression Logic 9.8 Reset Conditions 9.9 Register Definitions 9.9.1 I2C Bus Monitor Register- IBMR 9.9.2 I2C Data Buffer Register- IDBR 9-24 Intel PXA26x Processor Family Developers Manual 9.9.3 I2C Control Register- ICR The processor uses the bits in the I2C Control Register (ICR) to control the I2C unit. Table 9-10. I2C Data Buffer Register - IDBR (Sheet 2 of 2) Table 9-11. I2C Control Register - ICR (Sheet 1 of 3) Intel PXA26x Processor Family Developers Manual 9-25 Table 9-11. I2C Control Register - ICR (Sheet 2 of 3) 9-26 Intel PXA26x Processor Family Developers Manual 9.9.4 I2C Status Register Table 9-11. I2C Control Register - ICR (Sheet 3 of 3) Intel PXA26x Processor Family Developers Manual 9-27 Table 9-12. I2C Status Register - ISR (Sheet 1 of 2) 9-28 Intel PXA26x Processor Family Developers Manual 9.9.5 I2C Slave Address Register- ISAR Table 9-12. I2C Status Register - ISR (Sheet 2 of 2) Table 9-13. I2C Slave Address Register - ISAR Universal Asynchronous Receiver/ Transmitter 10 10.1 Feature List 10.2 Overview 10.2.1 Full Function UART 10.2.2 Bluetooth UART 10.2.3 Standard UART 10.2.4 Compatibility with 16550 10.3 Signal Descriptions 10.4 UART Operational Description 10.4.1 Reset 10.4.2 Internal Register Descriptions 10-6 Intel PXA26x Processor Family Developers Manual 10.4.2.1 Receive Buffer Register (RBR) Table 10-2. UART Register Addresses as Offsets of a Base Table 10-3. Receive Buf fe r Reg i s ter RBR 10.4.2.2 Transmit Holding Register (THR) 10.4.2.3 Divisor Latch Registers (DLL and DLH) ----------------------------------= BaudRate 14.7456MHz 16xDivisor() 10.4.2.4 Interrupt Enable Register (IER) Page 10.4.2.5 Interrupt Identification Register (IIR) Intel PXA26x Processor Family Developers Manual 10-11 Table 10-8. Interrupt Conditions Table 10-9. Interrupt Identification Register IIR 10-12 Intel PXA26x Processor Family Developers Manual 10.4.2.6 FIFO Control Register (FCR) Table 10-10. Interrupt Identification Register Decode Intel PXA26x Processor Family Developers Manual 10-13 Table 10-11. FIFO Control Register FCR 10-14 Intel PXA26x Processor Family Developers Manual 10.4.2.7 Line Control Register (LCR) 10.4.2.8 Line Status Register (LSR) 10-16 Intel PXA26x Processor Family Developers Manual Table 10-13. Line Status Register LSR (Sheet 1 of 2) Intel PXA26x Processor Family Developers Manual 10-17 10.4.2.9 Modem Control Register (MCR) Table 10-13. Line Status Register LSR (Sheet 2 of 2) 10-18 Intel PXA26x Processor Family Developers Manual Table 10-14. Modem Control Register MCR (Sheet 1 of 2) 10.4.2.10 Modem Status Register (MSR) 10-20 Intel PXA26x Processor Family Developers Manual 10.4.2.11 Scratchpad Register (SPR) 10.4.3 FIFO Interrupt Mode Operation 10.4.3.1 Receive Interrupt 10.4.3.2 Character Timeout Indication Interrupt 10.4.3.3 Transmit Interrupt 10.4.4 FIFO Polled Mode Operation 10.4.5 DMA Requests 10.4.5.1 Trailing Bytes in the Receive FIFO 10.4.6 Slow Infrared Asynchronous Interface 10.4.6.1 Infrared Selection Register (ISR) 10-24 Intel PXA26x Processor Family Developers Manual 10.4.6.2 Operation Table 10-17. Infrared Selection Register ISR Page 10.5 Register Summary Intel PXA26x Processor Family Developers Manual 10-27 10.5.1 UART Register Differences The default descriptions for BTMCR, BTMSR and STMCR are modified as shown in Table10-21. Table 10-20. STUART Register Locations Table 10-19. BTUART Register Locations Table 10-21. Flow Control Registers in BTUART and STUART Page Fast Infrared Communication Port 11 11.1 Signal Description 11.2 Fast Infrared Communications Port Operation 11.2.1 Four-Position Pulse Modulation 11.2.2 Frame Format 11.2.3 Address Field 11.2.4 Control Field 11.2.5 Data Field 11.2.6 CRC Field 11.2.7 Baud Rate Generation 11.2.8 Receive Operation 11.2.9 Transmit Operation 11.2.10 Transmit and Receive FIFOs 11.2.11 Trailing or Error Bytes in the Receive FIFO 11.3 Fast Infrared Communications Port Register Descriptions 11.3.1 FICP Control Register 0 Intel PXA26x Processor Family Developers Manual 11-9 Table 11-2. Fast Infrared Communication Port Control Register 0 (Sheet 1 of 2) 11-10 Intel PXA26x Processor Family Developers Manual 11.3.2 FICP Control Register 1 Table 11-2. Fast Infrared Communication Port Control Regi st er 0 (Sheet 2 of 2) 11.3.3 FICP Control Register 2 11.3.4 FICP Data Register 11.3.5 FICP Status Register 0 11-14 Intel PXA26x Processor Family Developers Manual 11.3.6 FICP Status Register 1 Table 11-6. Fast Infrared Communication Port Status Register 0 Intel PXA26x Processor Family Developers Manual 11-15 Table 11-7. Fast Infrared Communication Port Status Register 1 11.4 Fast Infrared Communications Port Register Locations Universal Serial Bus Device Controller 12 12.1 Universal Serial Bus Overview 12.2 Device Configuration 12.3 Universal Serial Bus Protocol 12.3.1 Signalling Levels 12.3.2 Bit Encoding 12.3.3 Field Formats 12.3.4 Packet Formats 12.3.4.1 Token Packet Type 12.3.4.2 Start of Frame Packet Type 12.3.4.3 Data Packet Type 12.3.4.4 Handshake Packet Type 12.3.5 Transaction F ormats 12.3.5.1 Bulk Transaction Type 12.3.5.2 Isochronous Transaction Type 12.3.5.3 Control Transaction Type 12.3.5.4 Interrupt Transaction Type 12.3.6 UDC Device Requests 12.3.7 Configuration 12.4 UDC Hardware Connection 12.4.1 Self-Powered Device 12.4.1.1 When GPIOn and GPIOx are Different Pins 12.4.1.2 When GPIOn and GPIOx are the Same Pin 12.4.2 Bus-Powered Devices 12.5 UDC Operation 12.5.1 Case 1: EP0 Control Read 12.5.2 Case 2: EP0 Control Read with a Premature Status Sta ge 12.5.3 Case 3: EP0 Control Write With or Without a Premature Status Stage 12.5.4 Case 4: EP0 No Data Command 12.5.5 Case 5: EP1 Data Transmit (BULK-IN) 12.5.5.1 Software Enables the DMA 12.5.5.2 Software Enables the EP1 Interrupt 12.5.6 Case 6: EP2 Data Receive (BULK-OUT) 12.5.6.1 Software Enables the DMA: 12.5.6.2 Software Allows the Core to Handle the Transaction 12.5.7 Case 7: EP3 Data Transmit (ISOCHRONOUS-IN) 12.5.7.1 Software Enables DMA 12.5.7.2 Software Enables the EP3 Interrupt 12.5.7.3 Software Enables the SOF Interrupt 12.5.8 Case 8: EP4 Data Receive (ISOCHRONOUS-OUT) 12.5.8.1 Software Enables the DMA 12.5.8.2 Software Allows the Core to Handle the Transaction 12.5.8.3 Software Enables the SOF Interrupt 12.5.9 Case 9: EP5 Data Transmit (INTERRUPT-IN) 12.5.10 Case 10: RESET Interrupt 12.5.11 Case 11: SUSPEND Interrupt 12.5.12 Case 12: RESUME Interrupt 12.6 UDC Register Descriptions 12.6.1 UDC Control Register 12.6.1.1 UDC Enable 12.6.1.2 UDC Active 12.6.1.3 UDC Resume (RSM) 12.6.1.4 Resume Interrupt Request (RESIR) 12.6.1.7 Reset Interrupt Request (RSTIR) 12.6.1.8 Reset Interrupt Mask (REM) 12.6.2 UDC Endpoint 0 Control/Status Register (UDCCS0) 12.6.2.1 OUT Packet Ready (OPR) 12.6.2.2 IN Packet Ready (IPR) Page 12-26 Intel PXA26x Processor Family Developers Manual 12.6.3 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 1, 6, or 11 12.6.3.1 Transmit FIFO Service (TFS) Table 12-13. UDC Endpoint 0 Control Status Register 12.6.3.2 Transmit Packet Complete (TPC) 12.6.3.3 Flush Tx FIFO (FTF) 12.6.3.4 Transmit Underrun (TUR) 12.6.3.5 Sent STALL (SST) 12.6.3.6 Force STALL (FST) 12.6.4 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 2, 7, or 12 Table 12-14. UDC Endpoint x Control Status Register, Where x is 1, 6 or 11 12.6.4.1 Receive FIFO Service (RFS) 12.6.4.2 Receive Packet Complete (RPC) 12.6.4.3 Bit 2 Reserved 12.6.4.4 DMA Enable (DME) 12.6.4.5 Sent Stall (SST) 12.6.4.7 Receive FIFO Not Empty (RNE) 12.6.4.8 Receive Short Packet (RSP) 12.6.5 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 3, 8, or 13 12.6.5.1 Transmit FIFO Service (TFS) 12.6.5.2 Transmit Packet Complete (TPC) Page Intel PXA26x Processor Family Developers Manual 12-33 12.6.6 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 4, 9, or 14 12.6.6.1 Receive FIFO Service (RFS) Table 12-16. UDC Endpoint x Control Status Register, Where x is 3, 8, or 13 Page Intel PXA26x Processor Family Developers Manual 12-35 12.6.7 UDC Endpoint x Control/Status Register (UDCCSx), Where x is 5, 10, or 15. 12.6.7.1 Transmit FIFO Service (TFS) Table 12-17. UDC Endpoint x Control Status Register, Where x is 4, 9, or 14 12.6.7.2 Transmit Packet Complete (TPC) 12.6.7.3 Flush Tx FIFO (FTF) 12.6.7.4 Transmit Underrun (TUR) 12.6.7.5 Sent STALL (SST) 12.6.7.6 Force STALL (FST) 12.6.8 UDC Interrupt Control Register 0 (UICR0) Table 12-18. UDC Endpoint x Control Status Register, Where x is 5, 10, or 15 12.6.8.1 Interrupt Mask Endpoint x (IMx), Where x is 0 through 7 12.6.9 UDC Interrupt Control Register 1 (UICR1) Intel PXA26x Processor Family Developers Manual 12-39 12.6.9.1 Interrupt Mask Endpoint x (IMx), where x is 8 through 15. 12.6.10 UDC Status/Interrupt Register 0 (USIR0) 12.6.10.1 Endpoint 0 Interrupt Request (IR0) 12.6.10.2 Endpoint 1 Interrupt Request (IR1) 12.6.10.3 Endpoint 2 Interrupt Request (IR2) 12.6.10.4 Endpoint 3 Interrupt Request (IR3) 12.6.11 UDC Status/Interrupt Register 1 (USIR1) 12.6.11.1 Endpoint 8 Interrupt Request (IR8) Page 12.6.12 UDC Frame Number High Register (UFNHR) 12.6.12.1 UDC Frame Number MSB (FNMSB) 12.6.12.2 Isochronous Packet Error Endpoint 4 (IPE4) 12.6.12.3 Isochronous Packet Error Endpoint 9 (IPE9) 12.6.12.4 Isochronous Packet Error Endpoint 14 (IPE14) 12.6.12.5 Start of Frame Interrupt Mask (SIM) 12.6.12.6 Start of Frame Interrupt Request (SIR) 12.6.13 UDC Frame Number L ow Register (UFNLR ) 12.6.14 UDC Byte Count Register x (UBCRx), Where x is 2, 4, 7, 9, 12, or 14. 12.6.14.1 Endpoint x Byte Count (BC[7:0]) 12.6.15 UDC Endpoint 0 Data Register (UDDR0) 12.6.16 UDC Data Register x (UDDRx), Where x is 1, 6, or 11 12.6.17 UDC Data Register x (UDDRx), Where x is 2, 7, or 12 12.6.18 UDC Data Register x (UDDRx), Where x is 3, 8, or 13 12.6.19 UDC Data Register x (UDDRx), Where x is 4, 9, or 14 12.6.20 UDC Data Register x (UDDRx), Where x is 5, 10, or 15 12-50 Intel PXA26x Processor Family Developers Manual 12.6.21 UDC Register Locations Intel PXA26x Processor Family Developers Manual 12-51 Table 12-32. UDC Control, Data, and Status Register Locations (Sheet 2 of 2) Page AC97 Controller Unit 13 13.1 Overview 13.2 Feature List 13.3 Signal Description 13.3.1 Signal Configuration Steps 13.3.2 Example AC-link 13.4 AC-link Digital Serial Interface Protocol 13.4.1 AC-link Audio Output Frame (SDATA_OUT) Page 13.4.1.1 Slot 0: Tag Phase 13.4.1.2 Slot 1: Command Address Port 13.4.1.3 Slot 2: Command Data Port 13.4.1.4 Slot 3: PCM Playback Left Channel 13.4.1.5 Slot 4: PCM Playback Right Channel 13.4.1.6 Slot 5: Modem Line Codec 13.4.1.7 Slots 6-11: Reserved 13.4.2 AC-link Audio Input Frame (SDATA_IN) 13.4.2.1 Slot 0: Tag Phase SYNC SDATA_IN BIT_CLK 13.4.2.2 Slot 1: Status Address Port/SLOTREQ bits Page 13.4.2.9 Slot 12: I/O Status 13.5 AC-link Low Power Mode _ 13.5.1 Powering Down the AC-link SDATA OUT 13.5.2 Waking up the AC-link 13.5.2.1 Wake up triggered by the Codec 13.5.2.2 Wake Up Triggered by the ACUNIT 13.5.2.2.1 Cold AC97 Reset 13.5.2.2.2 Warm AC97 Reset 13.6 ACUNIT Operation 13.6.1 Initialization 13.6.2 Trailing bytes 13.6.3 Operational Flow for Accessing Codec Registers 13.7 Clocks and Sampling Frequencies 13.8 Functional Description 13.8.1 FIFOs 13.8.2 Interrupts 13.8.3 Registers 13.8.3.1 Register Mapping Summary 13.8.3.2 Global Control Register 13-20 Intel PXA26x Processor Family Developers Manual Table 13-8. Global Control Register (Sh eet 1 of 2) Table 13-7. Register Mapping Summary (Sheet 2 of 2) Intel PXA26x Processor Family Developers Manual 13-21 Table 13-8. Global Control Register (Sheet 2 of 2) 13-22 Intel PXA26x Processor Family Developers Manual 13.8.3.3 Global Status Register (GSR) Table 13-9. Global Status Register (Sheet 1 of 2) Intel PXA26x Processor Family Developers Manual 13-23 Table 13-9. Global Status Register (Sheet 2 of 2) 13-24 Intel PXA26x Processor Family Developers Manual 13.8.3.4 PCM-Out Control Register (POCR) 13.8.3.5 PCM-In Control Register (PICR) Table 13-10. PCM-Out Control Register Table 13-11. PCM-I n Co n tr o l Re g i ster (PICR) Intel PXA26x Processor Family Developers Manual 13-25 13.8.3.6 PCM-Out Status Register (POSR) 13.8.3.7 PCM_In Status Register (PISR) Table 13-12. PCM-Out Status Register Table 13-13. PCM_In Status Register 13-26 Intel PXA26x Processor Family Developers Manual 13.8.3.8 Codec Access Register (CAR) 13.8.3.9 PCM Data Register (PCDR) Table 13-14. Codec Access Register Table 13-15. PCM Data Regi st er 13.8.3.10 Mic-In Control Register (MCCR) 13-28 Intel PXA26x Processor Family Developers Manual 13.8.3.11 Mic-In Status Register (MCSR) 13.8.3.12 Mic-In Data Register (MCDR) Table 13-17. Mic-In Status Register Table 13-18. Mic-In Data Register 13.8.3.13 Modem-Out Control Register (MOCR) Intel PXA26x Processor Family Developers Manual 13-29 Figure 13-10. Mic-in Receive-Only Operation Table 13-19. Modem-Out Control Register 13-30 Intel PXA26x Processor Family Developers Manual 13.8.3.14 Modem-In Control Register (MICR) 13.8.3.15 Modem-Out Status Register (MOSR) Table 13-20. Modem-In Control Register Table 13-21. Modem-Ou t St atus Register Intel PXA26x Processor Family Developers Manual 13-31 13.8.3.16 Modem-In Status Register (MISR) 13.8.3.17 Modem Data Register (MODR) Table 13-22. Modem-In Status Register Table 13-23. Modem Data Register 13.8.3.18 Accessing Codec Registers Intel PXA26x Processor Family Developers Manual 13-33 Table 13-24. Address Mapping for Codec Registers (Shee t 1 of 2) 13-34 Intel PXA26x Processor Family Developers Manual Table 13-24. Address Mapping for Codec Registers (Sheet 2 of 2) Inter-Integrated Circuit Sound Controller 14 14.1 Overview 14.2 Signal Descriptions 14.3 Controller Operation 14.3.1 Initialization 14.3.2 Disabling and Enabling Audio Replay 14.3.3 Disabling and Enabling Audio Record 14.3.4 Transmit FIFO Errors 14.3.5 Receive FIFO Errors 14.3.6 Trailing Bytes 14.4 Serial Audio Clocks and Sampling Frequencies 14.5 Data Formats 14.5.1 FIFO and Memory Format 14.5.2 I2S and MSB-Justified Serial Audio Formats 14.6 I2S Controller Register Descriptions 14.6.1 Serial Audio Controller Global Control Register (SACR0) Intel PXA26x Processor Family Developers Manual 14-9 14.6.1.1 Special purpose FIFO Read/Write function Table 14-3. SACR0 Bit Descriptions (Sheet 2 of 2) 14.6.1.2 Suggested TFTH and RFTH for DMA servicing 14.6.2 Serial Audio Controller I2S/MSB-Justified Control Register (SACR1) Intel PXA26x Processor Family Developers Manual 14-11 14.6.3 Serial Audio Controller I2S/MSB-Justified Status Register (SASR0) Table 14-6. SACR1 Bit Descriptions 14-12 Intel PXA26x Processor Family Developers Manual Table 14-7. SASR0 Bit Descriptions 14.6.4 Serial Audio Clock Divider Register (SADIV) 14.6.5 Serial Audio Interrupt Clear Register (SAICR) 14.6.6 Serial Audio Interrupt Mask Register (SAIMR) 14.6.7 Serial Audio Data Register (SADR) 14.6.8 Controller: Register Memory Map 14.7 Interrupts MultiMediaCard Controller 15 15.1 Overview Page Page 15.2 MultiMediaCard Controller Functional Description 15.2.1 Signal Description 15.2.2 MultiMediaCard Controller Reset 15.2.3 Card Initialization Sequence 15.2.4 MMC and SPI Modes 15.2.4.1 MMC Mode 15.2.4.2 SPI Mode 15.2.5 Error Detection 15.2.6 Interrupts 15.2.7 Clock Control 15.2.8 Data FIFOs 15.2.8.1 Response Data FIFO (MMC_RES) 15.2.8.2 Receive Data FIFO, MMC_RXFIFO 15.2.8.3 Transmit Data FIFO, MMC_TXFIFO 15.2.8.4 DMA and Program I/O 15.3 Card Communication Protocol 15.3.1 Basic, No Data, Command and Response Sequence 15.3.2 Data Transfer 15.3.2.1 Block Data Write 15.3.2.2 Block Data Read Page 15.3.3 Busy Sequence 15.4 MultiMediaCard Controller Operation 15.4.1 Start and Stop Clock 15.4.2 Initialize 15.4.3 Enabling SPI Mode 15.4.4 No Data Command and Response Sequence 15.4.5 Erase 15.4.6 Single Data Block Write 15.4.7 Single Block Read 15.4.8 Multiple Block Write 15.4.9 Multiple Block Read 15.4.10 Stream Write 15.4.11 Stream Read 15.5 MultiMediaCard Controller Register Descriptions 15.5.1 MMC_STRPCL Register 15-22 Intel PXA26x Processor Family Developers Manual 15.5.2 MMC_STAT Register Table 15-6. MMC_STRPCL Register Table 15-7. MMC_STAT Register (Sheet 1 of 2) Intel PXA26x Processor Family Developers Manual 15-23 15.5.3 MMC_CLKRT Register Table 15-7. MMC_STAT Register (Sheet 2 of 2) 15-24 Intel PXA26x Processor Family Developers Manual 15.5.4 MMC_SPI Register The MMC_SPI register is for SPI mode only and is set by the softwar e. Table 15-8. MMC_CLK Reg ister Table 15-9. MMC_SPI Register (Sheet 1 of 2) Intel PXA26x Processor Family Developers Manual 15-25 15.5.5 MMC_CMDAT Register Table 15-9. MMC_SPI Register (Sheet 2 of 2) Table 15-10. MMC_CMDAT Register (Sheet 1 of 2) 15-26 Intel PXA26x Processor Family Developers Manual 15.5.6 MMC_RESTO Register Table 15-10. MMC_CMDAT Register (Sheet 2 of 2) 15.5.7 MMC_RDTO Register 15.5.8 MMC_BLKLEN Register 15.5.9 MMC_NOB Register 15.5.10 MMC_PRTBUF Register Intel PXA26x Processor Family Developers Manual 15-29 15.5.11 MMC_I_MASK Register The MMC_I_MASK register masks off the various interrupts when set to a 1 (see Table 15-16). Table 15-15. MMC_PRTBUF Register Table 15-16. MMC_I_MASK Register 15-30 Intel PXA26x Processor Family Developers Manual 15.5.12 MMC_I_REG Register Table 15-16. MMC_I_MASK Register Intel PXA26x Processor Family Developers Manual 15-31 15.5.13 MMC_CMD Register Table 15-17. MMC_I_REG Register 15-32 Intel PXA26x Processor Family Developers Manual Table 15-18. MMC_CMD Reg i ster Table 15-19. Command Index Values (Sheet 1 of 3) Intel PXA26x Processor Family Developers Manual 15-33 Table 15-19. Command Index Values (Sheet 2 of 3) 15.5.14 MMC_ARGH Register 15.5.15 MMC_ARGL Register 15.5.16 MMC_RES FIFO (read only) 15.5.17 MMC_RXFIFO FIFO (read only) 15.5.18 MMC_TXFIFO FIFO Page Network/Audio Synchronous Serial Protocol Serial Ports 16 16.1 Overview 16.2 Features 16.3 Signal Description 16.4 Operation 16.4.1 Processor and DMA FIFO Access 16.4.2 Trailing Bytes in the Receive FIFO 16.4.2.1 Time-out 16.4.3 Data Formats 16.4.3.1 TI Synchronous Serial Protocol* Details 16.4.3.2 SPI Protocol Details Page 16.4.3.2.1 Serial Clock Phase (SPH) 16.4.3.3 Microwire* Protocol Details 16.4.3.4 PSP Details Page 16-12 Intel PXA26x Processor Family Developers Manual Figure 16-10. Programmable Serial Protocol (single transfers) Table 16-2. Programmable Serial Protocol (PSP) Parameters 16.4.4 Hi-Z on SSPTXD 16.4.4.1 TI Synchronous Serial Port 16.4.4.2 Motorola SPI 16.4.4.3 National Semiconductor Microwire 16.4.4.4 Programmable Serial Protocol 16-16 Intel PXA26x Processor Family Developers Manual Figure 16-16. PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (master to frame) Figure 16-17. PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=1 (must be slave to frame) 16.4.5 FIFO Operation 16.4.6 Baud-Rate Generation 16.5 SSP Port Register Descriptions 16.5.1 SSP Control Register 0 (SSCR0) Intel PXA26x Processor Family Developers Manual 16-19 Table 16-3. SSCR0 Bit Definitions (Sheet 1 of 2) 16-20 Intel PXA26x Processor Family Developers Manual Table 16-3. SSCR0 Bit Definitions (Sheet 2 of 2) Intel PXA26x Processor Family Developers Manual 16-21 16.5.2 SSP Control Register 1 (SSCR1) 16-22 Intel PXA26x Processor Family Developers Manual Table 16-4. SSCR1 Bit Definitions (Sheet 2 of 6) Intel PXA26x Processor Family Developers Manual 16-23 Table 16-4. SSCR1 Bit Definitions (Sheet 3 of 6) 16-24 Intel PXA26x Processor Family Developers Manual Table 16-4. SSCR1 Bit Definitions (Sheet 4 of 6) Intel PXA26x Processor Family Developers Manual 16-25 Table 16-4. SSCR1 Bit Definitions (Sheet 5 of 6) 16-26 Intel PXA26x Processor Family Developers Manual Table 16-4. SSCR1 Bit Definitions (Sheet 6 of 6) Intel PXA26x Processor Family Developers Manual 16-27 16.5.3 SSP Programmable Serial Protocol Register (SSPSP) 16-28 Intel PXA26x Processor Family Developers Manual 16.5.4 SSP Time Out Register (SSTO) Table 16-5. SSPSP Bit Definitions (Sheet 2 of 2) 16.5.5 SSP Interrupt Test Register (SSITR) 16.5.6 SSP Status Register (SSSR) Intel PXA26x Processor Family Developers Manual 16-31 Table 16-8. SSSR Bit Definitions (Sheet 1 of 3) 16-32 Intel PXA26x Processor Family Developers Manual Table 16-8. SSSR Bit Definitions (Sheet 2 of 3) Intel PXA26x Processor Family Developers Manual 16-33 Table 16-8. SSSR Bit Definitions (Sheet 3 of 3) 16.5.7 SSP Data Register (SSDR) 16.6 Register Summary Intel PXA26x Processor Family Developers Manual 16-35 Table 16-10. NSSP Register Address Map Table 16-11. ASSP Register Address Map Page Hardware UART 17 17.1 Overview 17.2 Features 17.3 Signal Descriptions 17.4 Operation Page 17.4.1 Reset 17.4.2 FIFO Operation 17.4.2.1 FIFO Interrupt Mode Operation 17.4.2.1.3 Transmit Interrupt 17.4.2.2 FIFO Polled Mode Operation 17.4.2.3 FIFO DMA Mode Operation 17.4.2.4 DMA Receive Programming Errors 17.4.2.5 DMA Error Handling 17.4.3 Autoflow Control 17.4.4 Auto-Baud-Rate Detection Latch Register High (DLH ) registers 3 (ABR[ABT]) to select 17.4.5 Slow Infrared Asynchronous Interface 17.4.5.1 Operation 17.5 Hardware UART Register Descriptions 17.5.1 Receive Buffer Register (RBR) 17.5.2 Transmit Holding Register (THR) 17.5.3 Divisor Latch Registers (DLL and DLH) BaudRate 14.7456MHz 16xDivisor() ----------------------------------= 17.5.4 Interrupt Enable Register (IER) 17.5.5 Interrupt Identification Register (IIR) Intel PXA26x Processor Family Developers Manual 17-15 Table 17-7. Interrupt Conditions Table 17-8. IIR Bit Definitions (Sheet 1 of 2) 17-16 Intel PXA26x Processor Family Developers Manual Table 17-8. IIR Bit Definitions (Sheet 2 of 2) Table 17-9. Interrupt Identification Register Decode (Sheet 1 of 2) Intel PXA26x Processor Family Developers Manual 17-17 17.5.6 FIFO Control Register (FCR) definitions are shown in Table17-10 on page 17-17. Table 17-9. Interrupt Identification Register Dec ode (Sheet 2 of 2) Table 17-10. FCR Bit Definitions (Sheet 1 of 2) 17-18 Intel PXA26x Processor Family Developers Manual 17.5.7 Receive FIFO Occupancy Register (FOR) Table 17-10. FCR Bit Definitions (Sheet 2 of 2) 17.5.8 Auto-Baud Control Register (ABR) 17.5.9 Auto-Baud Count Register (ACR) definitions are shown in Table17-13 on page17-21. 17.5.10 Line Control Register (LCR) 17-22 Intel PXA26x Processor Family Developers Manual Table 17-14. LCR Bit Definitions (Sheet 1 of 2) 17.5.11 Line Status Register (LSR) 17-24 Intel PXA26x Processor Family Developers Manual Intel PXA26x Processor Family Developers Manual 17-25 Table 17-15. LSR Bit Definitions (Sheet 2 of 3) 17-26 Intel PXA26x Processor Family Developers Manual 17.5.12 Modem Control Register (MCR) Table 17-15. LSR Bit Definitions (Sheet 3 of 3) Intel PXA26x Processor Family Developers Manual 17-27 Table 17-16. MCR Bit Definitions (Sheet 1 of 2) 17.5.13 Modem Status Register (MSR) The MSR bit definitions are shown in Table17-17 on page 17-29. Intel PXA26x Processor Family Developers Manual 17-29 Note: When bit 0, 1, 2, or 3 is set, a Modem Status interrupt is genera ted if IER[MIE] is set. 17.5.14 Scratchpad Register (SPR) definitions are shown in Table17-18. Table 17-17. MSR Bit Definitions Table 17-18. SPR Bit Definitions 17-30 Intel PXA26x Processor Family Developers Manual 17.5.15 Infrared Selection Register (ISR) Intel PXA26x Processor Family Developers Manual 17-31 17.6 Hardware UART Register Summary Table17-20 contains the register addresses for the HWUART. Table 17-19. ISR Bit Definitions (Sheet 2 of 2) Table 17-20. HWUART Register Locations (Sheet 1 of 2) 17-32 Intel PXA26x Processor Family Developers Manual Table 17-20. HWUART Regi st er Locations (Sheet 2 of 2) Internal Flash 18 18.1 Initialization 18.1.1 Intel StrataFlash Memory Reset Configuration 18.1.2 BOOT_SEL[2:0] Configuration 18.1.3 Determining the Size and Configuration of Flash Using Software 18.1.4 SXCNFG Configuration 18.1.5 Configuring the Intel StrataFlash Memory 18-4 Intel PXA26x Processor Family Developers Manual Intel PXA26x Processor Family Developers Manual 18-5 18-6 Intel PXA26x Processor Family Developers Manual 18.2 Additional Intel StrataFlash Memory Information