Intel PXA26X 5.1.7 Byte Transfer Order

5-10 Intel® PXA26x Processor Family Developer’s Manual
Direct Memory Access Controller
5.1.7 Byte Transfer Order
The DCMD[ENDIAN] bit indicates the byte ordering in a word when data is read from or written
to memory. Refer to F i gure5-5 on page 5-10 for details. The DCMD[ENDIAN} bit must be set to
0, which is little endian transfers.
Figure5-5, “Little Endian Transfers” on page 5-10 shows the order which data is transferred as
determined by the DCMD[ENDIAN] and DCMD[SIZE] bits.
If data is being transferred from an internal device to memo ry, DCMD[ENDIAN] is set to a 0, and
DCMD[SIZE] is set to a 1, the memory receives the data in this order:
1. Byte[0]
2. Byte[1]
3. Byte[2]
4. Byte[3]
Figure 5-5. Little Endian Transfers
D[31] D[0]
from memory
321 0
DMAC
From
ToTo
From
3
2
1
03
2
1
0
10
10
32
32
Half-Word Wide
Device Byte Wide
Device
Little Endian DMA Transf er s
321 0
To/Fr om
Word Wide
Device