xviii Intel® PXA26x Processor Family Developer’s Manual
Contents
4-49 OS Timer Register Locations..................................................................................................4-42
4-50 PWM_CTRLn Bit Definitions...................................................................................................4-45
4-51 PWM_DUTYn Bit Definitions..................................................... ... ...........................................4-46
4-52 PWM_PERVALn Bit Definitions...............................................................................................4-47
4-53 PWM Register Locations........................................................ ............................................. ....4-48
5-1 DMAC Signal List......................................................................................................................5-3
5-2 Channel Priority (if all channels are running concurrently)........................................................5-5
5-3 Channel Priority.........................................................................................................................5-5
5-4 Priority Schemes Examples................................... ....................................................................5-5
5-5 DMA Quick Reference for Internal Peripherals................................................................. ......5-13
5-6 DINT Register Bitmap and Bit Definitions................................................................................5-17
5-7 DMA Channel Control/Status Register Bitmap and Bit Definitions..........................................5-18
5-8 DRCMRx Registers Bitmap Bit Definitions..............................................................................5-20
5-9 DMA Descriptor Address Register Bit Definitions....................................................................5-21
5-10 DSADRx Register Bitmap Bit Definitions............................ .....................................................5-22
5-11 DTADRx Register Bitmap Bit Definitions.................................................................................5-23
5-12 DCMDx Register Bitmap and Bit Definitions...........................................................................5-24
5-13 DMA Controller Registers........................................................................................................5-28
6-1 Device Transactions..................................................................................................................6-7
6-2 Memory Interface Control Registers..........................................................................................6-8
6-3 MDCNFG Register Bitmap and Bit Definitions........................................................ ..................6-9
6-4 MDMRS Register Bitmap........................................................................................................6-12
6-5 MDMRSLP Register Bit Definitions.........................................................................................6-14
6-6 MDREFR Register Bitmap.......................................................................................................6-15
6-7 Sample SDRAM Memory Size Options...................................................................................6-18
6-8 External to Internal Address Mapping for Normal Bank Addressing.......................................6-19
6-9 External to Internal Address Mapping for SA-1111 Addressing..............................................6-21
6-10 Pin Mapping to SDRAM Devices with Normal Bank Addressing.............................................6-22
6-11 Pin Mapping to SDRAM Devices with SA-1111 Addressing ...................................................6-24
6-12 SDRAM Command Encoding..................................................................................................6-26
6-13 SDRAM Mode Register Opcode Table....................................................................................6-26
6-14 SXCNFG Register Bitmap.......................................................................................................6-30
6-15 SXCNFG Register Bitmap.......................................................................................................6-35
6-16 Synchronous Static Memory External to Internal Address Mapping Options..........................6-35
6-17 SXMRS Register Bitmap.........................................................................................................6-36
6-18 Read Configuration Register Programming Values.................................................................6-39
6-19 Frequency Code Configuration Values Based on Clock Speed........................................ ......6-39
6-20 32-Bit Bus Write Access..........................................................................................................6-41
6-21 16-Bit Bus Write Access..........................................................................................................6-42
6-22 32-Bit Byte Address Bits MA[1:0] for Reads Based on DQM[3:0]...........................................6-43
6-23 16-Bit Byte Address Bit MA[0] for Reads Based on DQM[1:0]................................................6-43
6-24 SA-1111 Register Bit Definitions.............................................................................................6-43
6-25 MSC0/1/2 Register Bit Definitions....................................................... ....................................6-45
6-26 Asynchronous Static Memory and Variable Latency I/O Capabilities......................................6-47
6-27 MCMEMx Register Bitmap......................................................................................................6-58
6-28 MCATTx Register Bitmap................................................ ........................................................6-58
6-29 MCIOx Register Bitmap...........................................................................................................6-59
6-30 Card Interface Command Assertion Code Table.....................................................................6-59
6-31 MECR Configuration Register Bitmap.....................................................................................6-61
6-32 Common Memory Space Write Commands............................................................................6-63