Intel PXA26X 12.6.15 UDC Endpoint 0 Data Register (UDDR0)

12-46 Intel® PXA26x Processor Family Developer’s Manual
Universal Serial Bus Device Controller
12.6.15 UDC Endpoint 0 Data Register (UDDR0)
The UDC endpoint 0 data register is a 16-entry by 8-bit bidirectional FIFO. When the host
transmits data to the UDC Endpoint 0, the core reads the UDC endpoint 0 register to access the
data. When the UDC sends data to the host, the core writes the data to be sent in the UDC endpoi nt
0 register. The core can only read and write the FIFO at specific points in a control sequence. The
direction that the FIFO flows is controlled by the UDC. Normally, the UDC is in an idle state,
waiting for the host to send commands. When the host sends a command, the UDC fills the FIFO
with the command from the host and the core reads the command from the FIFO when it arrives.
The only time the core may write the endpoint 0 FIFO is after a valid command from the host is
received and it requires a transmission in response.
Table 12-25. UDC Byte Count Register x, Where x is 2, 4, 7, 9, 12, or 14
0h 4060 0068 UBCR2 Read-Only
0h 4060 006C UBCR4 Read-Only
0h 4060 0070 UBCR7 Read-Only
0h 4060 0074 UBCR9 Read-Only
0h 4060 0078 UBCR12 Read-Only
0h 4060 007C UBCR14 Read-Only
Bit 31:8 7 6 5 4 3 2 1 0
Reserved BC[7:0]
Reset X 0 0 0 0 0 0 0 0
Bits Name Description
7:0 BC BYTE COUNT (read-only):
Number of bytes in the FIFO is Byte Count plus 1 (BC+1).
31:8 — Reserved for future use