Intel PXA26X 16.4.3.2.1 Serial Clock Phase (SPH)

16-8 Intel® PXA26x Processor Family Developer’s Manual
Network/Audio Synchronous Serial Protocol Serial Ports
The state of SSPRXD is undefined before the MSB and after the LSB is transmitted. For minimum
power consumption, this pin must not float.
16.4.3.2.1 Serial Clock Phase (SPH)
The phase relationship between the SSPSCLK and the serial frame (SSPSFRM) pins when the
Motorola SPI* protocol is selecte d is controlled by SSCR1[SPH].
When SPH is cleared, SSPSCLK remains in its inactive or idle state (as determined by
SSCR1[SPO]) for one full cycle after SSPSFRM is asserted low at the beginning of a frame.
SSPSCLK continues to transition for the rest of the frame. It is then held in its inactive state for
one-half of an SSPSCLK period be fore SSPSFRM is de-asserted high at the end of the frame.
When SPH is set, SSPSCLK remains in its inactive or idle state (as determined by S SCR1[SPO])
for one-half cycle after SSPSFRM is asserted low at the be gin ning of a fr ame. SS PSCLK con tin ues
to transition for the remainder of the frame and is then held in its inact ive state for one full
SSPSCLK period before SSPSFRM is de-asserted high at the end of the frame.
The combination of the SSCR1[SPO] and SSCR1[SPH] settings determine when SSP SCLK is
active during the assertion of SSPSFRM and which SSPSCLK edge transmits and receives data on
the SSPTXD and SSPRXD pins.
When programming SSCR1[SPO] and SSCR1[SPH] to the same value (both set or both cleared),
transmit data is driven on the falling edge of SSPSCLK and receive data is latched on the rising
edge of SSPSCLK. When programmi ng SSCR1[SPO] and SSCR1[SPH] to opposite values (one
set and the other cleared), transmit data is driven on the rising edge of SSPSCLK and rece ive data
is latched on the falling edge of SSPSCLK.
Note: SSCR1[SPH] is ignored for all data frame formats except for the Motorola SPI* protocol.
Figure16-6 shows the pin timing for all four programming combinations of SSCR1[SPO] and
SSCR1[SPH]. The SSCR1[SPO] invert s the polarity of the SSPSCLK sig nal and SSCR1[SPH]
determines the phase relationship between SSPSCLK and SSPSFRM, shifting the SSPSCLK
signal one-half phase to the left or right during the asser tion of SSPSFRM.
Figure 16-5. Motorola SPI* Frame Protocols for SPO and SPH Programming (multiple
transfers)
A9652-01
SSPRXD
SSPSFRM
SSPSCLK SPO=0
SSPSCLK SPO=1
SSPTXD
MSB 4 to 32 Bits LSB
Bit[N] Bit[N-1] Bit[1] Bit[0]
Bit[N] Bit[N-1] Bit[1] Bit[0]
Undefined Undefined
End of Transfer Data State