Intel PXA26X 16.4.1 Processor and DMA FIFO Access, 16.4.2 Trailing Bytes in the Receive FIFO

Intel® PXA26x Processor Family Developer’s Manual 16-3

Network/Audio Synchronous Serial Protocol Serial Ports

16.4.1 Processor and DMA FIFO Access

The CPU or DMA accesses data through the SSP ports transmit and receive FI FOs. A CPU access

takes the form of programmed I/O, transferring one FIFO entry per access. The FIFO are seen as

one 32-bit location by the processor. CPU accesses are normally triggered by an SSSR interrupt

and are always 32-bits wide. CPU writes to the FIFOs ignore bits beyond the programmed FIF O

data size (EDSS/DSS value); and CPU reads return zeroes in the MSBs down to the programmed

data size.

The FIFOs can also be accessed by DMA bursts (in m ultiples of one, two or four bytes) depending

upon the EDSS value. When SSCR0[EDSS] is set, DMA bursts must be in mul tiples of four bytes

(the DMA must have the SSP port configured as a 32-bit peripheral).When SSCR0[EDSS] is

cleared, DMA bursts must be in multiples of one or two bytes (the DMA’s DCMD[WIDTH]

If the DMA DCMD[WIDTH] field is configured f or 1 byte w idt h, the DMA bur st size m ust be 8 or

16.

For writes, the SSP port takes the data from the transmit FIFO, serializes it, and sends it over the

serial wire (SSPTXD) to the external device. Receive data from the external device (on SSPRXD)

is converted to parallel words and stored in the receive FIFO.

When exceeded, a programmable trigger threshold generates an interr upt or DMA service request

that, if SSCR1[TIE] or SSCR1[TSRE] are enabled, signal the CPU or DMA, respectively, to refill

the transmit FIFO. Similarly, a programmable tri gger threshold generates an interrupt or DMA

service request that, if SSCR1[RIE] or SSCR1[RSRE] are enabled, signal the CPU or DMA,

respectively, to empty the receive FIFO.

The receive and transmit FIFOs are differentiated by whether the access is a read or a write

transfer. Reads automatically target the receive FIFO, while writes write data to the transmi t FIFO.

From a memory-map perspective, both reads and writes are at the same address. The FIFOs are 16

samples deep by one word wide.

16.4.2 Trailing Bytes in the Receive FIFO

When the number of samples in the receive FIFO is less than the trigger threshold and no

additional data is received, the remaining bytes are called trailing bytes. Trailing bytes must be

handled by the processor. Trailing bytes are identified via a time-out mechanism and the existence

of data within the receive FIFO.

A time-out condition exists when the receive FIFO is idle for the period of time defined by the

Time-Out Register (SSTO). When a time-out oc curs, t he recei ver time- out in ter rupt (S SSR[ TINT] )

is set. If the time-out interrupt is enabled (SSCR1[TINTE] set) a time -out in terru pt occur s to si gnal

the processor that a time-out condition has occurred. The time-out timer is reset after receiving a

new sample or after the processor reads the receive FIFO. Once SSSR[TINT] is set it must be

cleared by writing a one to it. If the time-out interrupt is enabled, clearin g SS CR1[TINTE] also

causes the time-out interrupt to be de-asserted.