Intel® PXA26x Processor Family Developer’s Manua l xvii
Contents
3-26 CCLKCFG Bit Definitions.........................................................................................................3-40
3-27 PWRMODE Bit Definitions........................... .... ........................................... ... ..........................3-41
4-1 GPIO Alternate Functions..........................................................................................................4-3
4-2 GPIO Register Definitions..........................................................................................................4-7
4-3 GPLR0 Bit Definitions................................................................................................................4-8
4-4 GPLR1 Bit Definitions................................................................................................................4-9
4-5 GPLR2 Register Bitmap............................................................................................................4-9
4-6 GPDR0 Bit Definitions................................................................... ..........................................4-10
4-7 GPDR1 Bit Definitions................................................................... ..........................................4-10
4-8 GPDR2 Register Bitmap..........................................................................................................4-10
4-9 GPSR0 Bit Definitions..............................................................................................................4-11
4-10 GPSR1 Bit Definitions..............................................................................................................4-11
4-11 GPSR2 Register Bitmap..........................................................................................................4-12
4-12 GPCR0 Bit Definitions................................................................... ..........................................4-12
4-13 GPCR1 Bit Definitions................................................................... ..........................................4-12
4-14 GPCR2 Register Bitmap........................................ .... ..............................................................4-13
4-15 GRER0 Bit Definitions.............................................................................................................4-14
4-16 GRER1 Bit Definitions.............................................................................................................4-14
4-17 GRER2 Register Bitmap..........................................................................................................4-14
4-18 GFER0 Bit Definitions..............................................................................................................4-15
4-19 GFER1 Bit Definitions..............................................................................................................4-15
4-20 GFER2 Register Bitmap..........................................................................................................4-15
4-21 GEDR0 Bit Definitions................................................................... ..........................................4-16
4-22 GEDR1 Bit Definitions................................................................... ..........................................4-17
4-23 GEDR2 Register Bitmap........................................ .... ..............................................................4-17
4-24 GAFR0_L Bit Definitions..........................................................................................................4-18
4-25 GAFR0_U Bit Definitions.........................................................................................................4-18
4-26 GAFR1_L Bit Definitions..........................................................................................................4-19
4-27 GAFR1_U Bit Definitions.........................................................................................................4-19
4-28 GAFR2_L Bit Definitions..........................................................................................................4-20
4-29 GAFR2_U Register Bitmap......................................................................................................4-20
4-30 GPIO Register Addresses.......................................................................................................4-21
4-31 ICMR Register Bitmap.............................................................................................................4-25
4-32 ICLR Register Bitmap..............................................................................................................4-25
4-33 ICCR Bit Definitions.................................................................................................................4-26
4-34 ICIP Register Bitmap...............................................................................................................4-27
4-35 ICFP Register Bitmap..............................................................................................................4-27
4-36 ICPR Register Bitmap..............................................................................................................4-28
4-37 List of First–Level Interrupts....................................................................................................4-30
4-38 Interrupt Controller Register Addresses..................................................... ... ..........................4-31
4-39 RTTR Bit Definitions................................................................................................................4-33
4-40 RTAR Bit Definitions................................................................................................................4-34
4-41 RCNR Bit Definitions...............................................................................................................4-34
4-42 RTSR Bit Definitions................................................................................................................4-35
4-43 RTC Register Addresses.........................................................................................................4-38
4-44 OSMR[x] Bit Definitions.......................................................... .................................................4-39
4-45 OIER Bit Definitions.................................................................................................................4-40
4-46 OWER Bit Definitions...............................................................................................................4-40
4-47 OSCR Bit Definitions...............................................................................................................4-41
4-48 OSSR Bit Definitions................................................................................................................4-42