Intel PXA26X 1.2 System Integration Features

1-2 Intel® PXA26x Processor Family Developer’s Manual
Introduction
1.2 System Integration Features
The PXA26x processor family features are:
•Integrated synchronous Intel StrataFlash® memory on some versions
•Single-ended universal serial bus client interface
•Network synchronous serial protocol port
•Audio synchronous serial protocol port
•Low voltage support (2.775 volts) for VCCQ
•Low voltage support (2.5 volts) for VCCN
•Memory controller
•Clock and power control lers
•Universal serial bus client
•DMA controller
•LCD controller
•AC97
•I2S
•MultiMediaCard
•FIR communication
•Synchronous serial protocol port
•I2C
•General purpose I/O pins
•Four UARTs, one with hardware flow control
•Real-time clock
•OS timers
•Pulse width modulati on
•Interrupt control
1.2.1 Memory Controller
The memory controller provides glueless control signals with programmable timing for a wide
assortment of memory-chip types and organizations. It supports up to four SDRAM partitions; six
static chip selects for SRAM, SSRAM, flash, ROM, SROM, and companion chips; as well as
support for two PCMCIA or Compact Flash slots
1.2.2 Clocks and Power Controllers
The PXA26x processor family functional blocks are driv en by clocks that are derived from a
3.6864-MHz crystal and an optional 32.768-KHz crystal.