Intel PXA26X 16.5 SSP Port Register Descriptions

16-18 Intel® PXA26x Processor Family Developer’s Manual
Network/Audio Synchronous Serial Protocol Serial Ports
16.5 SSP Port Register Descriptions
Each SSP port consists of seven registers: three control, one d ata, one stat us, one time-ou t , and one
test.
•The SSP control registers (SSCR0, SSCR1) c onfig ure th e baud r ate, data l eng th, frame for mat,
data-transfer mechanism, and port enabling. They also permit settin g the FIFO trigger
threshold that triggers an interrupt.
•Access all registers using aligned words.
Note: Write the SSP port registers after a reset but before the SSP port is enabled.
•The SSP Time-Out (SSTO) register programs the time-out value use d to signal a specified
period of receive FIFO inactivity.
•While in PSP mode, the SSP Programma ble Serial Protocol (SSPSP) registe r programs the
parameters used in defining the data transfer .
•The data register is mapped as one 32-bit location, which physically points to either of two 32-
bit registers: one register is for writes of data transfers to the transmit FI FO and the other
register is for reads that take data from the receive FIFO. A write cycle or burst write puts
successive words into the SSP write register and then into the transmit FIFO. A read cycle or
burst read takes data from the SSP read register and the receive FIFO reloads it with available
data bits it has stored.
Do not increment the address using read and write DMA bursts.
•Besides showing the state of the FIFO buffers, the sta tus register shows whether the
programmable trigger threshold has been passed and whether a transmit or receive FIFO
service request is active. The status register also shows how full the FIFO is. Flag bits ind icate
when the SSP port is actively transmitting data, when the transmit FIF O is not full, and when
the receive FIFO is not empty. The SSSR[ROR] bit signals an overrun of the receive FIFO In
this case newly received data is discarded.
When programming registers, reserved bits must be writt en as zeroes and read as undefined.
16.5.1 SSP Control Register 0 (SSCR0)
SSCR0, shown in Table16-3, contains bit fields that control various functions within the SSP port.
Before enabling the SSP port (via SSE) the desired values for this register must be set.
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.