Intel PXA26X 14.4 Serial Audio Clocks and Sampling Frequencies

Intel® PXA26x Processor Family Developer’s Manual 14-5
Inter-Integrated Circuit Sound Controller
Asserting the DREC bit in SACR1 has the following effects:
1. I2SLINK recording activity is disabled. The frame or data sample, in the mids t of which the
recording is disabled, could have invalid data (some data bits will be over-written with zeros) .
To avoid this, disable record only after the transfer of valid data.
2. Receive FIFO pointers are reset to zero.
3. Receive FIFO fill-level is reset to zero.
4. Any read operations by the DMA/CPU are returned with zeros.
5. Receive DMA requests are disabled.
14.3.4 Transmit FIFO Errors
A status bit is set during transmit under-run cond iti ons. If enabl ed, thi s can trig ger an int err up t. For
further details, see Section14.6.3, Section 14.6.6 and Section 14.6.5. During transmit under-run
conditions, the last valid sample is continuously sent out across the I2SLINK. Transmit under-run
can occur under the following conditions:
1. Valid transmit data is still available in mem ory, but the DMA controller starves the transmit
FIFO, as it is busy servicing other higher-pri ority peripherals.
2. The DMA controller has transferred all valid data from memory to the transmit FIFO.
The second condition prompts for the last valid sample to be ec hoed across the I2SLINK until the
I2SC is turned off by disabling the SACR0[ENB] bit.
14.3.5 Receive FIFO Errors
A status bit is set during receive over-run conditions. If enabled, this can trigger an interrupt. For
further details, see Section14.6.3, Section 14.6.6 and Section 14.6.5. During receive over-run
conditions, data sent by the CODEC is lost (will not be recorded).
14.3.6 Trailing Bytes
When the CODEC has completed transmitting valid data, zeros will be recorded by the I2SC, and
this will continue until the unit is turned off by disabling the SACR0[ENB] bit.
If the total buffer size of the received data is less than a factor of the receive thre s hold, zeross will
be recorded. A receive DMA request is made when the programmed threshold is reached.
14.4 Serial Audio Clocks and Sampling Frequencies
The BITCLK is the rate at which audio data bits enter or leave the I2SLINK. SYSCLK is required
by the CODEC to run delta sigma ADC operations.
BITCLK can be supplied either by the CODEC or by an internal PLL. If supplied internally,
BITCLK and SYSCLK are configured as output pins, and both are supplied to the CODEC. If
BITCLK is supplied by the CODEC, then it is configured as an input pin. In th is case, the
SYSCLK’s GPIO pin can be used for an alternate function.