5-4 Intel® PXA26x Processor Family Developer’s Manual
Direct Memory Access Controller
The PREQ[37:0] bits are the active high internal signals from the on-chip peripher als . Unlike
DREQ[1:0], they are level sensitive. The DMAC does not sample the PREQ[37:0 ] signals until it
completely finishes the current data transfer. For a write request to on-chip peripheral, the DMAC
begins to sample the PREQ[37:0] signals after it sends the last byte of the write request. For a read
request, the DMAC begins to sample the PREQ[37:0] signals after it sends the last byt e that
pertains to the read on the internal bus.
The DCSR[REQPEND] bit indicates the status of the pending request for the channel.
If a DREQx assertion sets the DCSR[REQPEND] bit and software re sets the DCSR[RUN] bit to
stop the channel, the DCSR[REQPEND] bit and the internal registers that hold the DREQx
assertion information may remain set even though the channel has stopped. To reset the
DCSR[REQPEND] bit, software must send a dummy descriptor that transfers some data.

5.1.2.2 DMA_IRQ Signal

The processor has 16 IRQ signals, one for each DMA channel. Each DMA IRQ can be read in the
DINT register that is shown in Figure5-6, “DINT Register Bitmap and Bit Definitions” on page
5-17. The user can mask some bits that cause interrupts on a channel, such as ENDIRQEN,
STARTIRQEN, and STOPIRQEN.
When DMA interrupt occurs, it is visible in Pending Interrupt Register Bit 25 (see Section4.2.2.5,
“Interrupt Controller Pending Register (ICPR)” on page4-27). When a pending interrupt becomes
active, it is sent to the CPU if its corresponding ICMR mask Bi t 25 (see Section4.2.2.1, “Interrupt
Controller Mask Regist er (ICMR)” on page 4-24 ) is set to a one.
5.1.3 Direct Memory Access Channel Priority Scheme
The a DMA channel priority scheme allows peripherals th at require high bandwidth to be serviced
more often than those requiring less bandw idth. The DMA channel s are int ern ally di vide d into fo ur
sets. Each set contains four channels. The channels get a round-robin priority in each set. Set zero
has the highest priority. Set 1 has higher pr io rity th an sets tw o an d th ree. Sets two and thr ee are lo w
priority sets. Refer to Table 5-2 for details. High bandwidth peripheral s mus t be pro gr ammed in set
zero. Memory-to-memory moves and low bandwidth peripherals must be programmed in set two
or three. When all channels are running concurrently, set zero is serviced four times out of any
eight consecutive channel servicing instances. Set one is serviced twice and sets two and three are
each serviced once.
If two or more channels are active and request a DMA, the priority scheme in Table 5-2 applies.
Request priority does not affect requests that have already started. The DMAC priority scheme is
considered when the smaller dimension of the DCMDx[SIZE] or DCMDx[LENGTH] is complete.
If all channels request data transfers, the sets are prioritized in this or der:
•Set zero
•Set one
•Set zero
•Set two
•Set zero
•Set one