Intel PXA26X 8.7.3 SSP Data Register (SSDR)

Intel® PXA26x Processor Family Developer’s Manual 8-15
Synchronous Serial Port Controller
8.7.2.8 Receive FIFO Interrupt/DMA Threshold (RFT)
This 4-bit value sets the level at or above which the FIFO controller triggers a DMA service
interrupt and, if enabled, an interrupt request. Refer to Table 8-4 for suggested RFT values
associated with DMA servicing.
Be careful not to set the RFT value too hi gh for your system or the FIFO could overrun because of
the bus latencies caused by other internal and external peripherals. This is especially the case for
interrupt and polled modes that require a longer time to service.
Table 8-4. TFT and RFT Values for DMA Servicing
8.7.3 SSP Data Register (SSDR)
The SSP Data Register (SSDR) is a single address location that can be accessed by read/write data
transfers. Transfers can be single transfers, 4 half -word bursts, or 8 half-word bursts.
As the system accesses the register, FIFO control logic transfers data automatically between
register and FIFO as fast as the system moves data. The SSDR has status bits that indicate whether
either FIFO is full, above or below a programmable threshold, or empty.
For transmit operations from SSPC to SSP peripheral, the CPU may write the register when it is
below its threshold level and is using programmed I/O.
When a data size less than 16-bits is selected, do not left-justify data written to the transmit FIFO.
Transmit logic left-justifies the data and ignores any unused bits. Received data less than 16-bits is
automatically right-justified in the receive FIFO.
When the SSPC is programmed for National Microwire frame format and the size for tr ansmit dat a
is 8-bits, as selected by the MWDS bit in the SSCR1, the most significant byt e is ignored.
SSCR0[DSS] controls receive data size.
DMA Burst Size TFT Value RFT Value
Min Max Min Max
8 Bytes 0 11 3 15
16 Bytes 0 7 7 15