Intel PXA26X 13.6 ACUNIT Operation

13-14 Intel® PXA26x Processor Family Developer’s Manual
AC97 Controller Unit
13.5.2.2.1 Cold AC97 Reset
A cold reset is generated when the nACRESET pin is asserted through the GCR[COLD_RST].
Asserting and de-asserting nACRESET activates BITCLK (supplied by the codec) and
SDATA_OUT. All AC97 control registers are initialized to their default power on reset values.
nACRESET is an asynchronous AC97 input.
13.5.2.2.2 Warm AC97 Reset
A warm AC97 reset reactivates the AC-link without altering the current AC97 register values. A
warm reset is generated when BITCLK is absent and SYNC is driven high for a minimum of 1µs.
In normal audio frames, SYNC is a synchronous AC97 input. When BITCLK is absent, SYNC is
treated as an asynchronous input used to generate a warm reset to AC97.
The ACUNIT must not activate BITCLK until it samples SYNC low again. This prevents a new
audio frame from being falsely detected.
When the ACUNIT receives a wake-up from the codec, it issues an interrupt (if the interr upt on
resume is enabled). Software must then issue a warm or cold reset to the codec by setting the
appropriate bit in the GCR.
13.6 ACUNIT Operation
The ACUNIT can be accessed through the processor or the DMA controller. The processor uses
programmed I/O instructions to access the ACUNIT and can access four register types:
•ACUNIT registers: Accessible at 32-bit boundaries. They are listed in Section13.8.3,
“Registers” on page13-18.
•Codec registers: An audio or modem codec can contain up to sixty-four 16-bit registers. A
codec uses a 16-bit address boundary for registers. The ACUNIT supplies access to the codec
registers by mapping them to its 32-bit address domain boundary. Section1 3.8.3.18,
“Accessing Codec Registers” on page13-32 describes the mapping from the 32-bit to 16-bit
boundary. A write or read operation that targets th ese registers is sent across the AC-link.
•Modem codec GPIO register: If the ACUNIT is connected to a modem codec, t he codec G PI O
register can also be accessed. The codec GPIO register uses access address 0x0054 in the
codec domain. The GPIO write operation goes across the AC-link but a read does not. The
register contents are continuously updated into a register in the controller domain when a
frame is received from the codec. When the processor tries to read the codec GPIO register,
this shadow register is read instead.
•ACUNIT FIFO data: The ACUNIT has two transmit FIFOs for audio-out and modem-out and
three receive FIFOs for audio-in, modem-in, and Mic-in. The transmit FIFOs ar e written by
writing either the PCM Data Register (PCDR) or the Modem Data Register (MOD R). Rece ive
FIFO entries are read through the PCDR, the MODR, or the Mic-in Data Register (MCDR).