13-28 Intel® PXA26x Processor Family Developer’s Manual

AC97 Controller Unit
13.8.3.11 Mic-In Status Register (MCSR)13.8.3.12 Mic-In Data Register (MCDR)

The Mic-In Data Register is a read-only register . A w rite t o this reg ister h as no ef fect . A r ead to this

register gets a 32-bit sample from the mic-in receive FIFO.

Table 13-17. Mic-In Status Register

Physical Address
4050_0018 MCSR Register AC97
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
FIFOE
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
31:5 — Reserved
4FIFOE
FIFO ERROR (FIFOE):
0 – No receive FIFO error has occurred.
1 – A receive FIFO error occurred. This bit is set if a receive FIFO overrun occurs. In this
case, the FIFO pointers don't increment, the incoming data from the AC-link is not
written into the FIFO and will be lost. This could happen due to DMA controller having
excessive bandwidth requirements and hence not being able to flush out the receive
FIFO in time.
Bit is cleared by writing a 1 to this bit position.
3:0 — Reserved

Table 13-18. Mic-In Data Register

Physical Address
4050_0060 MCDR Register AC97
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved MIC_IN_DAT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
31:16 — Reserved
15:0 MIC_IN_DAT Mic-in data