15-8 Intel® PXA26x Processor Family Developer’s Manual
MultiMediaCard Controller
3. Restart the clock.
Software must not stop the clock when it attempts to read the receive FIFOs or write the transm it
FIFOs. When the clock stops, it resets the pointers in the FIFOs and any data left in the FIFOs can
not be transmitted or accessed. When the receive FIFOs are empty and the
MMC_STAT[DATA_TRAN_DONE] is set, software may stop the clock.
The software can specify the clock divisor of the 20-Mhz clock by setting the MMC_CLKRT
register. The clock rate may be set as follows:
•20Mhz
•1/2 of 20Mhz, 10 Mhz
•1/4 of 20Mhz, 5 Mhz
•1/8 of 20Mhz, 2.5 Mhz
•1/16 of 20Mhz, 1.25 Mhz
•1/32 of 20Mhz, 625 Khz
•1/64 if 20Mhz, 312.5 Khz
The controller can also turn the clock off automatically. If both receive FIFOs become full during
data reads, or one receive FIFO is being read by the software and the other receive FIFO becomes
full, or both transmit FIFOs become empty during data writes, or one tr ansmit FIFO is being
written by the software and the other transm it FIFO is empty, the controller will automatically turn
the clock off to prevent data overflows and underruns. For read data transfers, the controller turns
the clock back on after a receive FIFO has been emptied. For write data transfers, the contr oller
turns the clock back on after the transmit FIFO is no longer empty .
Warni ng: Stopping the clock while data is in the transmit or receive FIFO s wi ll cause unpredictable results.
If the software stops the clock at any time, it must wait for the MMC_ STAT[CLK_EN] status bit to
be cleared before proceeding.
15.2.8 Data FIFOs
The controller FIFOs for the response tokens, received data, and trans mitted data are MMC_RES,
MMC_RXFIFO, and MMC_TXFIFO, respectively. These FIFOs are accessible by the softw are
and are described in the following paragraphs.

15.2.8.1 Response Data FIFO (MMC_RES)

The response FIFO, MMC_RES, contains the response received from an MMC card after a
command is sent from the controller. MMC_RES is a rea d only, 16-bit, and 8-entry deep FIFO.
The FIFO will hold all possible response lengths. R espon ses t hat are o nly on e byte lo ng a re located
on the MSB of the 16-bit entry in the FIFO. The first half-word read from the response FIFO is the
most significant half-word of the received response.
The FIFO does not contain the response CRC. The status of the CRC check is in the status register ,
MMC_STAT.