4 BIOS Setup Utility
CommPlete Communications Server 31
Chipset Features Setup
This section allows you to configure the system based on the specific features of the
installed chipset. The chipset manages bus speeds and access to system memory
resources, such as DRAM and the L2 external cache. It also coordinates
communications between the conventional ISA bus and the PCI bus. These items
should never need to be altered. The default settings have been chosen because they
provide the best operating conditions for your system. The only time you might
consider making any changes would be if you discovered that data was being lost
while using your system.

DRAM Timing

The first chipset settings deal with CPU access to dynamic random access memory
(DRAM). The DRAM timing should match the speed of the slowest installed memory.
For instance, if 60 ns SIMMs are installed on the RASCard, you should set this item to
60 ns. But if you install both 60 ns and 70 ns SIMMs, you should change it to 70 ns.

System BIOS Cacheable

When this item is enabled, accesses to the system BIOS ROM addressed at F0000H-
FFFFFH are cached, provided that the cache controller is enabled.
Enabled BIOS access cached.
Disabled BIOS access not cached (Default).